/linux/Documentation/devicetree/bindings/phy/ |
H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Kishon Vijay Abraham I <kishon@ti.com> 16 - ti,j721e-wiz-16g 17 - ti,j721e-wiz-10g 18 - ti,j721s2-wiz-10g 19 - ti,am64-wiz-10g [all …]
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H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Guido Günther <agx@sigxcpu.org> 13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the 18 in either MIPI-DSI PHY mode or LVDS PHY mode. 23 - fsl,imx8mq-mipi-dphy 24 - fsl,imx8qxp-mipi-dphy [all …]
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/linux/arch/arm64/boot/dts/xilinx/ |
H A D | zynqmp-clk-ccf.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 14 bootph-all; 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-frequency = <33333333>; 21 bootph-all; 22 compatible = "fixed-clock"; [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7ulp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2018 NXP 8 #include <dt-bindings/clock/imx7ulp-clock.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include "imx7ulp-pinfunc.h" 15 interrupt-parent = <&intc>; 17 #address-cells = <1>; 18 #size-cells = <1>; 37 #address-cells = <1>; [all …]
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/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-j784s4-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/mux/mux.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 12 #include "k3-serdes.h" 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 25 compatible = "mmio-sram"; [all …]
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H A D | k3-j721e-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 7 #include <dt-bindings/phy/phy.h> 8 #include <dt-bindings/phy/phy-ti.h> 9 #include <dt-bindings/mux/mux.h> 11 #include "k3-serdes.h" 14 cmn_refclk: clock-cmnrefclk { 15 #clock-cells = <0>; 16 compatible = "fixed-clock"; 17 clock-frequency = <0>; [all …]
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H A D | k3-j721s2-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/phy/phy-cadence.h> 9 #include <dt-bindings/phy/phy-ti.h> 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 21 compatible = "mmio-sram"; 23 #address-cells = <1>; [all …]
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H A D | k3-j7200-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 17 compatible = "mmio-sram"; 19 #address-cells = <1>; 20 #size-cells = <1>; 23 atf-sram@0 { 28 scm_conf: scm-conf@100000 { [all …]
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H A D | k3-j7200-mcu-wakeup.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 13 mbox-names = "rx", "tx"; 18 reg-names = "debug_messages"; 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8ulp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8ulp-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/power/imx8ulp-power.h> 10 #include <dt-bindings/thermal/thermal.h> 12 #include "imx8ulp-pinfunc.h" 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; [all …]
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H A D | imx8mm.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8mm-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/power/imx8mm-power.h> 11 #include <dt-bindings/reset/imx8mq-reset.h> 12 #include <dt-bindings/thermal/thermal.h> 14 #include "imx8mm-pinfunc.h" 17 interrupt-parent = <&gic>; [all …]
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H A D | imx8mq.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 7 #include <dt-bindings/clock/imx8mq-clock.h> 8 #include <dt-bindings/power/imx8mq-power.h> 9 #include <dt-bindings/reset/imx8mq-reset.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include "dt-bindings/input/input.h" 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interconnect/imx8mq.h> [all …]
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H A D | imx95.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 6 #include <dt-bindings/dma/fsl-edma.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/thermal/thermal.h> 12 #include "imx95-clock.h" 13 #include "imx95-pinfunc.h" 14 #include "imx95-power.h" 17 interrupt-parent = <&gic>; [all …]
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H A D | imx93.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx93-clock.h> 7 #include <dt-bindings/dma/fsl-edma.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/power/fsl,imx93-power.h> 12 #include <dt-bindings/thermal/thermal.h> 14 #include "imx93-pinfunc.h" 17 interrupt-parent = <&gic>; [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | brcm,cygnus-audio.txt | 4 - compatible : "brcm,cygnus-audio" 5 - #address-cells: 32bit valued, 1 cell. 6 - #size-cells: 32bit valued, 0 cell. 7 - reg : Should contain audio registers location and length 8 - reg-names: names of the registers listed in "reg" property 12 - clocks: PLL and leaf clocks used by audio ports 13 - assigned-clocks: PLL and leaf clocks 14 - assigned-clock-parents: parent clocks of the assigned clocks 16 - assigned-clock-rates: List of clock frequencies of the 17 assigned clocks [all …]
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H A D | nvidia,tegra-audio-graph-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Jon Hunter <jonathanh@nvidia.com> 16 - Sameer Pujar <spujar@nvidia.com> 19 - $ref: audio-graph.yaml# 24 - nvidia,tegra210-audio-graph-card 25 - nvidia,tegra186-audio-graph-card 27 clocks: [all …]
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H A D | nvidia,tegra210-ahub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 for audio pre-processing, post-processing and a programmable full 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 22 pattern: "^ahub@[0-9a-f]*$" 26 - enum: 27 - nvidia,tegra210-ahub [all …]
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H A D | nvidia,tegra210-dmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 16 - Jon Hunter <jonathanh@nvidia.com> 17 - Sameer Pujar <spujar@nvidia.com> 20 - $ref: dai-common.yaml# 24 pattern: "^dmic@[0-9a-f]*$" 28 - const: nvidia,tegra210-dmic 29 - items: [all …]
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H A D | nvidia,tegra186-dspk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 Density Modulation (PDM) transmitter that up-samples the input to 13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 21 - $ref: dai-common.yaml# 25 pattern: "^dspk@[0-9a-f]*$" [all …]
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H A D | nvidia,tegra210-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The Inter-IC Sound (I2S) controller implements full-duplex, 11 bi-directional and single direction point-to-point serial 16 - Jon Hunter <jonathanh@nvidia.com> 17 - Sameer Pujar <spujar@nvidia.com> 20 - $ref: dai-common.yaml# 24 pattern: "^i2s@[0-9a-f]*$" [all …]
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/linux/arch/mips/boot/dts/img/ |
H A D | pistachio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/pistachio-clk.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/mips-gic.h> 11 #include <dt-bindings/reset/pistachio-resets.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 19 interrupt-parent = <&gic>; 22 #address-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | ti,j721e-ufs.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vignesh Raghavendra <vigneshr@ti.com> 15 - const: ti,j721e-ufs 21 clocks: 23 description: phandle to the M-PHY clock 25 power-domains: 28 assigned-clocks: [all …]
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/linux/Documentation/devicetree/bindings/media/ |
H A D | mediatek,vcodec-encoder.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Yunfei Dong <yunfei.dong@mediatek.com> 20 - items: 21 - enum: 22 - mediatek,mt8173-vcodec-enc-vp8 23 - mediatek,mt8173-vcodec-enc 24 - mediatek,mt8183-vcodec-enc [all …]
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra186.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra186-clock.h> 3 #include <dt-bindings/gpio/tegra186-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/memory/tegra186-mc.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8 #include <dt-bindings/power/tegra186-powergate.h> 9 #include <dt-bindings/reset/tegra186-reset.h> 10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h> [all …]
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/linux/Documentation/devicetree/bindings/iio/adc/ |
H A D | nxp,imx8qxp-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Cai Huoqing <caihuoqing@baidu.com> 17 const: nxp,imx8qxp-adc 25 clocks: 28 clock-names: 30 - const: per 31 - const: ipg [all …]
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