/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mp-nominal.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 19 assigned-clock-rates = <0>, <0>, 24 fsl,operating-mode = "nominal"; 28 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 30 assigned-clock-rates = <800000000>; 34 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, [all …]
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H A D | imx8-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/dma/fsl-edma.h> 9 #include <dt-bindings/firmware/imx/rsrc.h> 11 dma_ipg_clk: clock-dma-ipg { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <120000000>; 15 clock-output-names = "dma_ipg_clk"; [all …]
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H A D | imx8ulp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8ulp-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/power/imx8ulp-power.h> 10 #include <dt-bindings/thermal/thermal.h> 12 #include "imx8ulp-pinfunc.h" 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; [all …]
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H A D | imx8-ss-img.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2019-2021 NXP 6 img_ipg_clk: clock-img-ipg { 7 compatible = "fixed-clock"; 8 #clock-cells = <0>; 9 clock-frequency = <200000000>; 10 clock-output-names = "img_ipg_clk"; 13 img_pxl_clk: clock-img-pxl { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; [all …]
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H A D | imx95.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 6 #include <dt-bindings/clock/nxp,imx95-clock.h> 7 #include <dt-bindings/dma/fsl-edma.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/thermal/thermal.h> 13 #include "imx95-clock.h" 14 #include "imx95-pinfunc.h" 15 #include "imx95-power.h" [all …]
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H A D | imx8-ss-lvds1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_lvds1>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_lvds1: interrupt-controller@57240000 { 15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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H A D | imx8mm-overdrive.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 7 assigned-clock-rates = <0>, <1000000000>; 11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 14 assigned-clock-rates = <0>, <1000000000>; 18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, 22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, 25 assigned-clock-rates = <750000000>,
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Kishon Vijay Abraham I <kishon@ti.com> 16 - ti,j721e-wiz-16g 17 - ti,j721e-wiz-10g 18 - ti,j721s2-wiz-10g 19 - ti,am64-wiz-10g [all …]
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/linux/arch/arm64/boot/dts/xilinx/ |
H A D | zynqmp-clk-ccf.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 #include "xlnx-zynqmp-clk.h" 13 pss_ref_clk: pss-ref-clk { 14 bootph-all; 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-frequency = <33333333>; 18 clock-output-names = "pss_ref_clk"; [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7ulp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2018 NXP 8 #include <dt-bindings/clock/imx7ulp-clock.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include "imx7ulp-pinfunc.h" 15 interrupt-parent = <&intc>; 17 #address-cells = <1>; 18 #size-cells = <1>; 37 #address-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | brcm,cygnus-audio.txt | 4 - compatible : "brcm,cygnus-audio" 5 - #address-cells: 32bit valued, 1 cell. 6 - #size-cells: 32bit valued, 0 cell. 7 - reg : Should contain audio registers location and length 8 - reg-names: names of the registers listed in "reg" property 12 - clocks: PLL and leaf clocks used by audio ports 13 - assigned-clocks: PLL and leaf clocks 14 - assigned-clock-parents: parent clocks of the assigned clocks 16 - assigned-clock-rates: List of clock frequencies of the 17 assigned clocks [all …]
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H A D | nvidia,tegra-audio-graph-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Jon Hunter <jonathanh@nvidia.com> 16 - Sameer Pujar <spujar@nvidia.com> 19 - $ref: audio-graph.yaml# 24 - nvidia,tegra210-audio-graph-card 25 - nvidia,tegra186-audio-graph-card 26 - nvidia,tegra264-audio-graph-card [all …]
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H A D | nvidia,tegra210-ahub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 for audio pre-processing, post-processing and a programmable full 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 22 pattern: "^ahub@[0-9a-f]*$" 26 - enum: 27 - nvidia,tegra210-ahub [all …]
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H A D | nvidia,tegra186-dspk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 Density Modulation (PDM) transmitter that up-samples the input to 13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 21 - $ref: dai-common.yaml# 25 pattern: "^dspk@[0-9a-f]*$" [all …]
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H A D | nvidia,tegra210-dmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 16 - Jon Hunter <jonathanh@nvidia.com> 17 - Sameer Pujar <spujar@nvidia.com> 20 - $ref: dai-common.yaml# 24 pattern: "^dmic@[0-9a-f]*$" 28 - const: nvidia,tegra210-dmic 29 - items: [all …]
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H A D | nvidia,tegra210-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The Inter-IC Sound (I2S) controller implements full-duplex, 11 bi-directional and single direction point-to-point serial 16 - Jon Hunter <jonathanh@nvidia.com> 17 - Sameer Pujar <spujar@nvidia.com> 20 - $ref: dai-common.yaml# 24 pattern: "^i2s@[0-9a-f]*$" [all …]
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/linux/arch/arm/boot/dts/microchip/ |
H A D | sama7g5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 #include <dt-bindings/interrupt-controller/irq.h> 14 #include <dt-bindings/interrupt-controller/arm-gic.h> 15 #include <dt-bindings/clock/at91.h> 16 #include <dt-bindings/dma/at91.h> 17 #include <dt-bindings/gpio/gpio.h> 18 #include <dt-bindings/mfd/at91-usart.h> 19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h> [all …]
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/linux/arch/mips/boot/dts/img/ |
H A D | pistachio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/pistachio-clk.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/mips-gic.h> 11 #include <dt-bindings/reset/pistachio-resets.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 19 interrupt-parent = <&gic>; 22 #address-cells = <1>; [all …]
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/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am65-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 7 #include <dt-bindings/phy/phy-am654-serdes.h> 11 compatible = "mmio-sram"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 atf-sram@0 { 21 sysfw-sram@f0000 { 25 l3cache-sram@100000 { 30 gic500: interrupt-controller@1800000 { [all …]
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/linux/drivers/clk/ |
H A D | clk-conf.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk-provider.h> 9 #include <linux/clk/clk-conf.h> 21 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents() 22 "#clock-cells"); in __set_clk_parents() 23 if (num_parents == -EINVAL) in __set_clk_parents() 24 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents() 28 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents() 29 "#clock-cells", index, &clkspec); in __set_clk_parents() 32 if (rc == -ENOENT) in __set_clk_parents() [all …]
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | ti,j721e-ufs.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vignesh Raghavendra <vigneshr@ti.com> 15 - const: ti,j721e-ufs 21 clocks: 23 description: phandle to the M-PHY clock 25 power-domains: 28 assigned-clocks: [all …]
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra186.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra186-clock.h> 3 #include <dt-bindings/gpio/tegra186-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/memory/tegra186-mc.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8 #include <dt-bindings/power/tegra186-powergate.h> 9 #include <dt-bindings/reset/tegra186-reset.h> 10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h> [all …]
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H A D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra210-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra210-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/reset/tegra210-car.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/tegra124-soctherm.h> 10 #include <dt-bindings/soc/tegra-pmc.h> [all …]
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/linux/Documentation/devicetree/bindings/iio/adc/ |
H A D | nxp,imx8qxp-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Cai Huoqing <caihuoqing@baidu.com> 17 const: nxp,imx8qxp-adc 25 clocks: 28 clock-names: 30 - const: per 31 - const: ipg [all …]
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/linux/Documentation/devicetree/bindings/rtc/ |
H A D | st,stm32-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com> 15 - st,stm32-rtc 16 - st,stm32h7-rtc 17 - st,stm32mp1-rtc 18 - st,stm32mp25-rtc 23 clocks: [all …]
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