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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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H A Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pci_hostbvar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * NO WARRANTY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
37 * PCI/PCIe-Gen1 Host Bridge definitions.
48 * PCI/PCIe-Gen1 endpoint-mode device quirks
51 /** No quirks */
69 * The purpose of this work-around is unclear; there is some
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H A Dbhnd_pci_hostb.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
18 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
22 * NO WARRANTY
26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
38 * Broadcom BHND PCI/PCIe-Gen1 PCI-Host Bridge.
43 * Host-level PCI operations are handled at the bhndb bridge level by the
75 /* Device driver work-around variations */
146 /* Apple BCM4331 board-specific quirks */
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/freebsd/sys/dev/ath/
H A Dif_ath_btcoex.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * NO WARRANTY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
82 * XXX TODO: There needs to be a PCIe workaround to disable ASPM if
90 struct ath_hal *ah = sc->sc_ah; in ath_btcoex_cfg_wb195()
98 device_printf(sc->sc_dev, "Enabling WB195 BTCOEX\n"); in ath_btcoex_cfg_wb195()
146 struct ath_hal *ah = sc->sc_ah; in ath_btcoex_cfg_wb225()
154 device_printf(sc->sc_dev, "Enabling WB225 BTCOEX\n"); in ath_btcoex_cfg_wb225()
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/freebsd/sys/dev/iwm/
H A Dif_iwm_pcie_trans.c13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
20 /*-
21 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
90 /*-
91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
82 #define AL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
87 #define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
93 #define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
101 #define AL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
106 #define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
116 #define AL_PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
117 #define AL_PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
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H A Dal_hal_pcie_w_reg.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
377 * cleared after MSI-X message associated with this specific interrupt
378 * bit is sent (MSI-X acknowledge is received).
379 * - Software can set a bit in this register by writing 1 to the
381 * Write-0 clears a bit. Write-1 has no effect.
382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically
393 * enabling software to generate a hardware interrupt. Write 0 has no
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/freebsd/usr.sbin/pciconf/
H A Dcap.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
16 * 3. Neither the name of the author nor the names of any co-contributors
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); in cap_power()
56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); in cap_power()
69 status = read_config(fd, &p->pc_se in cap_agp()
426 aspm_string(uint8_t aspm) aspm_string() argument
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/freebsd/sys/contrib/dev/athk/ath12k/
H A Dpci.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
36 /* BAR0 + 4k is always accessible, and no
38 * 4K - 32 = 0xFE0
68 "mhi-er0",
69 "mhi-er1",
86 "host2wbm-desc-feed",
87 "host2reo-re-injection",
88 "host2reo-command",
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/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
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H A Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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/freebsd/sys/arm64/rockchip/
H A Drk_pcie.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
78 #define ATU_OB_REGION_0_SIZE (( ATU_OB_REGIONS - 1) * ATU_OB_REGION_SIZE)
179 #define APB_WR4(_sc, _r, _v) bus_write_4((_sc)->apb_mem_res, (_r), (_v))
180 #define APB_RD4(_sc, _r) bus_read_4((_sc)->apb_mem_res, (_r))
240 {"rockchip,rk3399-pcie", 1},
258 val = bus_read_4(sc->apb_mem_res, base + reg); in rk_pcie_local_cfg_read()
261 val = bus_read_2(sc->apb_mem_res, base + reg); in rk_pcie_local_cfg_read()
264 val = bus_read_1(sc->apb_mem_res, base + reg); in rk_pcie_local_cfg_read()
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/freebsd/sys/dev/alc/
H A Dif_alc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
98 * enable MSI-X in alc_attach() depending on the card type. The operator can
248 nitems(alc_ident_table) - 1);
253 { -1, 0, 0 }
258 { -1, 0, 0 }
263 { -1, 0, 0 }
268 { -1, 0, 0 }
280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) in alc_miibus_readreg()
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/freebsd/sys/dev/wpi/
H A Dif_wpi.c1 /*-
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
317 for (ident = wpi_ident_table; ident->name != NULL; ident++) { in wpi_probe()
318 if (pci_get_vendor(dev) == ident->vendor && in wpi_probe()
319 pci_get_device(dev) == ident->device) { in wpi_probe()
320 device_set_desc(dev, ident->name); in wpi_probe()
339 sc->sc_dev = dev; in wpi_attach()
342 error = resource_int_value(device_get_name(sc->sc_dev), in wpi_attach()
343 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); in wpi_attach()
345 sc->sc_debug = 0; in wpi_attach()
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/freebsd/sys/dev/re/
H A Dif_re.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
59 * o 64-bit DMA
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
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/freebsd/sys/dev/iwn/
H A Dif_iwn.c1 /*-
2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr>
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
84 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" },
85 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" },
86 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" },
87 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" },
88 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" },
89 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" },
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
78- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
98 … (0x1<<0) // I/O space access enable. There are no I/O BARs supported.
116 … (0x1<<9) // Fast back-to-back transaction ena…
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