Home
last modified time | relevance | path

Searched +full:artpec8 +full:- +full:clk (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Daxis,artpec8-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC-8 SoC clock controller
10 - Jesper Nilsson <jesper.nilsson@axis.com>
13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
17 This external clock must be defined as a fixed-rate clock in dts.
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
26 'include/dt-bindings/clock/axis,artpec8-clk.h' header.
[all …]
/linux/drivers/clk/samsung/
H A Dclk-artpec8.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Common Clock Framework support for ARTPEC-8 SoC.
11 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/axis,artpec8-clk.h>
15 #include "clk.h"
16 #include "clk-exynos-arm64.h"
842 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
992 * artpec8_cmu_probe - Probe function for ARTPEC platform clocks
1000 struct device *dev = &pdev->dev; in artpec8_cmu_probe()
1003 exynos_arm64_register_cmu(dev, dev->of_node, info); in artpec8_cmu_probe()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o
8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o
9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o
10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o
11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o
12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
14 obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o
[all …]
/linux/drivers/tty/serial/
H A Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
21 * BJD, 04-Nov-2004
25 #include <linux/clk.h>
28 #include <linux/dma-mapping.h>
146 struct clk *clk; member
147 struct clk *baudclk;
165 #define portaddr(port, reg) ((port)->membase + (reg))
167 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
171 switch (port->iotype) { in rd_reg()
[all …]