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Searched +full:armada8k +full:- +full:pcie (Results 1 – 8 of 8) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmarvell,armada8k-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 7K/8K PCIe interface
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
13 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
20 - marvell,armada8k-pcie
22 - compatible
25 - $ref: snps,dw-pcie.yaml#
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H A Dpci-armada8k.txt1 * Marvell Armada 7K/8K PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
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H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/freebsd/sys/dev/pci/
H A Dpci_dw_mv.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* Armada 8k DesignWare PCIe driver */
98 {"marvell,armada8k-pcie", 1},
108 rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i])); in pci_mv_phy_init()
110 device_printf(sc->dev, "Cannot get phy[%d]\n", i); in pci_mv_phy_init()
118 if (sc->phy[i] == NULL) in pci_mv_phy_init()
120 rv = phy_enable(sc->phy[i]); in pci_mv_phy_init()
122 device_printf(sc->dev, "Cannot enable phy[%d]\n", i); in pci_mv_phy_init()
130 if (sc->phy[i] == NULL) in pci_mv_phy_init()
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H A Dpci_host_generic_fdt.c1 /*-
34 /* Generic ECAM PCIe driver FDT attachment */
95 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { in generic_pcie_fdt_probe()
100 device_set_desc(dev, "GEM5 PCIe host controller"); in generic_pcie_fdt_probe()
116 STAILQ_INIT(&sc->pci_ofw_devlist); in pci_host_generic_setup_fdt()
120 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); in pci_host_generic_setup_fdt()
121 if (parse_pci_mem_ranges(dev, &sc->base)) in pci_host_generic_setup_fdt()
129 if (sc->base.coherent == 0) { in pci_host_generic_setup_fdt()
130 sc->base.coherent = OF_hasprop(node, "dma-coherent"); in pci_host_generic_setup_fdt()
133 device_printf(dev, "Bus is%s cache-coherent\n", in pci_host_generic_setup_fdt()
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H A Dpci_host_generic_acpi.c1 /*-
32 /* Generic ECAM PCIe driver */
98 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK },
111 * generic_pcie_acpi_probe - look for root bridge flag
123 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; in generic_pcie_acpi_probe()
133 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
145 r = sc->base.nranges; in pci_host_generic_acpi_parse_resource()
146 switch (res->Type) { in pci_host_generic_acpi_parse_resource()
148 restype = res->Data.Address16.ResourceType; in pci_host_generic_acpi_parse_resource()
149 min = res->Data.Address16.Address.Minimum; in pci_host_generic_acpi_parse_resource()
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