1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
29 /* Armada 8k DesignWare PCIe driver */
98 	{"marvell,armada8k-pcie", 1},
108 		rv =  phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i]));  in pci_mv_phy_init()
110 			device_printf(sc->dev, "Cannot get phy[%d]\n", i);  in pci_mv_phy_init()
118 		if (sc->phy[i] == NULL)  in pci_mv_phy_init()
120 		rv = phy_enable(sc->phy[i]);  in pci_mv_phy_init()
122 			device_printf(sc->dev, "Cannot enable phy[%d]\n", i);  in pci_mv_phy_init()
130 		if (sc->phy[i] == NULL)  in pci_mv_phy_init()
132 		phy_release(sc->phy[i]);  in pci_mv_phy_init()
144 	reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG);  in pci_mv_init()
147 	pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg);  in pci_mv_init()
150 	pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511);  in pci_mv_init()
151 	pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311);  in pci_mv_init()
154 	pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002);  in pci_mv_init()
155 	pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002);  in pci_mv_init()
158 	reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1);  in pci_mv_init()
161 	pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg);  in pci_mv_init()
164 	pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF);  in pci_mv_init()
165 	pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0x0001FE00);  in pci_mv_init()
166 	pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0x00000000);  in pci_mv_init()
167 	pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF);  in pci_mv_init()
168 	pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF);  in pci_mv_init()
171 	pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0);  in pci_mv_init()
180 	cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1);  in pci_mv_intr()
181 	cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2);  in pci_mv_intr()
183 	pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1);  in pci_mv_intr()
184 	pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2);  in pci_mv_intr()
210 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in pci_mv_probe()
213 	device_set_desc(dev, "Marvell Armada8K PCI-E Controller");  in pci_mv_probe()
229 	sc->dev = dev;  in pci_mv_attach()
230 	sc->node = node;  in pci_mv_attach()
233 	sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,  in pci_mv_attach()
235 	if (sc->dw_sc.dbi_res == NULL) {  in pci_mv_attach()
243 	rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->dw_sc.dbi_res, &req,  in pci_mv_attach()
249 	rman_set_mapping(sc->dw_sc.dbi_res, &map);  in pci_mv_attach()
253 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,  in pci_mv_attach()
255 	if (sc->irq_res == NULL) {  in pci_mv_attach()
262 	rv = clk_get_by_ofw_name(sc->dev, 0, "core", &sc->clk_core);  in pci_mv_attach()
264 		device_printf(sc->dev, "Cannot get 'core' clock\n");  in pci_mv_attach()
269 	rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);  in pci_mv_attach()
271 		device_printf(sc->dev, "Cannot get 'reg' clock\n");  in pci_mv_attach()
276 	rv = clk_enable(sc->clk_core);  in pci_mv_attach()
278 		device_printf(sc->dev, "Cannot enable 'core' clock\n");  in pci_mv_attach()
283 	rv = clk_enable(sc->clk_reg);  in pci_mv_attach()
285 		device_printf(sc->dev, "Cannot enable 'reg' clock\n");  in pci_mv_attach()
301 	if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,  in pci_mv_attach()
302 		    pci_mv_intr, NULL, sc, &sc->intr_cookie)) {  in pci_mv_attach()