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/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
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H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM SMMUv3 Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
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/linux/Documentation/devicetree/bindings/display/
H A Darm,komeda.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/arm,komeda.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Komeda display processor
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
14 The Arm Mali D71 display processor supports up to two displays with up
21 - items:
22 - const: arm,mali-d32
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/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Miscellaneous Arm SMMU implementation and integration quirks
3 // Copyright (C) 2019 Arm Limited
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
28 static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page, in arm_smmu_read_ns() argument
33 return readl_relaxed(arm_smmu_page(smmu, page) + offset); in arm_smmu_read_ns()
36 static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page, in arm_smmu_write_ns() argument
41 writel_relaxed(val, arm_smmu_page(smmu, page) + offset); in arm_smmu_write_ns()
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_QCOM_IOMMU) += qcom_iommu.o
3 obj-$(CONFIG_ARM_SMMU) += arm_smmu.o
4 arm_smmu-objs += arm-smmu.o arm-smmu-impl.o arm-smmu-nvidia.o
5 arm_smmu-$(CONFIG_ARM_SMMU_QCOM) += arm-smmu-qcom.o
6 arm_smmu-$(CONFIG_ARM_SMMU_QCOM_DEBUG) += arm-smmu-qcom-debug.o
H A Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for ARM architected SMMU implementations.
5 * Copyright (C) 2013 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
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H A Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
12 #include "arm-smmu.h"
15 * Tegra194 has three ARM MMU-500 Instances.
18 * non-isochronous HW devices.
21 * In addition, the SMMU driver needs to coordinate with the memory controller
23 * memory client. This is necessary to allow for use-case such as seamlessly
30 * SMMU instance.
35 struct arm_smmu_device smmu; member
41 static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu) in to_nvidia_smmu() argument
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H A Darm-smmu-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL -1
19 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
21 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
24 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in qcom_smmu_tlb_sync() argument
30 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in qcom_smmu_tlb_sync()
32 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in qcom_smmu_tlb_sync()
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H A Darm-smmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * IOMMU API for ARM architected SMMU implementations.
5 * Copyright (C) 2013 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
18 #include <linux/io-64-nonatomic-hi-lo.h>
19 #include <linux/io-pgtable.h>
252 /* Maximum number of context banks per SMMU */
377 struct arm_smmu_device *smmu; member
383 struct mutex init_mutex; /* Protects smmu pointer */
389 struct arm_smmu_device *smmu; member
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H A Darm-smmu-qcom-debug.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "arm-smmu.h"
20 #include "arm-smmu-qcom.h"
59 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
61 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
64 void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) in qcom_smmu_tlb_sync_debug() argument
68 struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu); in qcom_smmu_tlb_sync_debug()
74 dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); in qcom_smmu_tlb_sync_debug()
76 cfg = qsmmu->cfg; in qcom_smmu_tlb_sync_debug()
80 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS], in qcom_smmu_tlb_sync_debug()
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/linux/drivers/iommu/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
35 depends on ARM || ARM64 || COMPILE_TEST
38 Enable support for the ARM long descriptor pagetable format.
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
55 depends on ARM || ARM64 || COMPILE_TEST
57 Enable support for the ARM Short-descriptor pagetable format.
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/linux/Documentation/devicetree/bindings/perf/
H A Darm,smmu-v3-pmcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm SMMUv3 Performance Monitor Counter Group
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
20 pattern: "^pmu@[0-9a-f]*"
23 - items:
24 - const: arm,mmu-600-pmcg
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3-sva.c1 // SPDX-License-Identifier: GPL-2.0
3 * Implementation of the IOMMU SVA API for the ARM SMMUv3
13 #include "arm-smmu-v3.h"
14 #include "../../io-pgtable-arm.h"
25 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_update_s1_domain_cd_entry()
26 list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) { in arm_smmu_update_s1_domain_cd_entry()
27 struct arm_smmu_master *master = master_domain->master; in arm_smmu_update_s1_domain_cd_entry()
30 cdptr = arm_smmu_get_cd_ptr(master, master_domain->ssid); in arm_smmu_update_s1_domain_cd_entry()
35 arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, in arm_smmu_update_s1_domain_cd_entry()
38 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_update_s1_domain_cd_entry()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
3 arm_smmu_v3-y := arm-smmu-v3.o
4 arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
5 arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o
7 obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) += arm-smmu-v3-test.o
H A Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for ARM architected SMMUv3 implementations.
5 * Copyright (C) 2015 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
32 #include "arm-smmu-v3.h"
33 #include "../../dma-iommu.h"
38 "Disable MSI-based polling for CMD_SYNC completion.");
81 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
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H A Darm-smmu-v3-test.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/io-pgtable.h>
8 #include "arm-smmu-v3.h"
26 static struct arm_smmu_device smmu = { variable
61 test_writer->test, sizeof(*entry_used_bits) * NUM_ENTRY_QWORDS, in arm_smmu_test_writer_record_syncs()
63 KUNIT_ASSERT_NOT_NULL(test_writer->test, entry_used_bits); in arm_smmu_test_writer_record_syncs()
67 test_writer->entry, in arm_smmu_test_writer_record_syncs()
68 NUM_ENTRY_QWORDS * sizeof(*test_writer->entry), in arm_smmu_test_writer_record_syncs()
71 test_writer->num_syncs += 1; in arm_smmu_test_writer_record_syncs()
72 if (!test_writer->entry[0]) { in arm_smmu_test_writer_record_syncs()
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/linux/drivers/acpi/arm64/
H A Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * IORT document number: ARM DEN 0049A
21 #include <linux/dma-map-ops.h>
45 * iort_set_fwnode() - Create iort_fwnode and use it to register
62 return -ENOMEM; in iort_set_fwnode()
64 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
65 np->iort_node = iort_node; in iort_set_fwnode()
66 np->fwnode = fwnode; in iort_set_fwnode()
69 list_add_tail(&np->list, &iort_fwnode_list); in iort_set_fwnode()
76 * iort_get_fwnode() - Retrieve fwnode associated with an IORT node
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/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
26 compatible = "arm,mhu", "arm,primecell";
31 #mbox-cells = <1>;
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux/drivers/iommu/arm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += arm-smmu/ arm-smmu-v3/
/linux/include/linux/
H A Dadreno-smmu-priv.h1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/io-pgtable.h>
12 * struct adreno_smmu_fault_info - container for key fault information
38 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
40 * @cookie: An opque token provided by adreno-smmu and passed
42 * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
54 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
55 * the GPU's SMMU instance. This is by necessity, as the GPU is directly
56 * updating the SMMU for context switches, while on the other hand we do
57 * not want to duplicate all of the initial setup logic from arm-smmu.
/linux/include/soc/tegra/
H A Dmc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/interconnect-provider.h>
14 #include <linux/reset-controller.h>
16 #include <linux/tegra-icc.h>
35 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
46 /* Tegra SMMU enable (Tegra210 and earlier) */
50 } smmu; member
104 void tegra_smmu_remove(struct tegra_smmu *smmu);
113 static inline void tegra_smmu_remove(struct tegra_smmu *smmu) in tegra_smmu_remove() argument
161 * @probe: Callback to set up SoC-specific bits of the memory controller. This is called
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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