Lines Matching +full:arm +full:- +full:smmu
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2021-2024 NVIDIA CORPORATION & AFFILIATES. */
8 #include <linux/dma-mapping.h>
17 #include "arm-smmu-v3.h"
68 /* -- PAGE0 -- */
85 /* -- PAGE1 -- */
93 /* VINTF logical-VCMDQ pages */
103 ((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
105 ((_vintf)->base + TEGRA241_VINTF_##_regname)
107 ((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
109 ((_vcmdq)->page1 + TEGRA241_VCMDQ_##_regname)
115 "This allows to disable CMDQV HW and use default SMMU internal CMDQ.");
123 * struct tegra241_vcmdq - Virtual Command Queue
154 * struct tegra241_vintf - Virtual Interface
158 * @hyp_own: Owned by hypervisor (in-kernel)
161 * @lvcmdq_mutex: Lock to serialize user-allocated lvcmdqs
186 * struct tegra241_vintf_sid - Virtual Interface Stream ID Mapping
201 * struct tegra241_cmdqv - CMDQ-V for SMMUv3
202 * @smmu: SMMUv3 device
215 struct arm_smmu_device smmu;
249 dev_err(cmdqv->dev, "%sfailed to %sable, STATUS=0x%08X\n",
268 snprintf(header, 16, "VINTF%u: ", vintf->idx);
269 return tegra241_cmdqv_write_config(vintf->cmdqv,
272 regval, header, &vintf->enabled);
279 if (WARN_ON(!vcmdq->vintf))
282 vcmdq->vintf->idx, vcmdq->idx, vcmdq->lidx);
290 return tegra241_cmdqv_write_config(vcmdq->cmdqv,
293 regval, h, &vcmdq->enabled);
300 struct iommufd_viommu *viommu = &vintf->vsmmu.core;
321 struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx];
324 __arm_smmu_cmdq_skip_err(&vintf->cmdqv->smmu, &vcmdq->cmdq);
338 /* Use readl_relaxed() as register addresses are not 64-bit aligned */
349 dev_warn(cmdqv->dev, "unexpected error reported. %s\n", err_str);
353 tegra241_vintf0_handle_error(cmdqv->vintfs[0]);
361 tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]);
372 switch (ent->opcode) {
383 tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu,
387 container_of(smmu, struct tegra241_cmdqv, smmu);
388 struct tegra241_vintf *vintf = cmdqv->vintfs[0];
395 /* Use SMMU CMDQ if VINTF0 is uninitialized */
396 if (!READ_ONCE(vintf->enabled))
406 lidx = raw_smp_processor_id() % cmdqv->num_lvcmdqs_per_vintf;
407 vcmdq = vintf->lvcmdqs[lidx];
408 if (!vcmdq || !READ_ONCE(vcmdq->enabled))
411 /* Unsupported CMD goes for smmu->cmdq pathway */
412 if (!arm_smmu_cmdq_supports_cmd(&vcmdq->cmdq, ent))
414 return &vcmdq->cmdq;
420 * When a guest-owned VCMDQ is disabled, if the guest did not enqueue a CMD_SYNC
424 * behavior in the new VM. Thus, a guest-owned VCMDQ must flush the TIMEOUT when
425 * it gets disabled. This can be done by just issuing a CMD_SYNC to SMMU CMDQ.
429 struct arm_smmu_device *smmu = &vcmdq->cmdqv->smmu;
439 arm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, cmd_sync, 1, true);
449 dev_err(vcmdq->cmdqv->dev,
465 dev_warn(vcmdq->cmdqv->dev,
470 dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h);
483 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));
487 dev_err(vcmdq->cmdqv->dev,
495 dev_dbg(vcmdq->cmdqv->dev, "%sinited\n", h);
499 /* Unmap a global VCMDQ from the pre-assigned LVCMDQ */
502 u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx)));
506 REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx)));
507 dev_dbg(vcmdq->cmdqv->dev, "%sunmapped\n", h);
512 u16 lidx = vintf->cmdqv->num_lvcmdqs_per_vintf;
516 while (lidx--) {
517 if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) {
518 tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]);
519 tegra241_vcmdq_unmap_lvcmdq(vintf->lvcmdqs[lidx]);
523 for (sidx = 0; sidx < vintf->cmdqv->num_sids_per_vintf; sidx++) {
529 /* Map a global VCMDQ to the pre-assigned LVCMDQ */
532 u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx)));
536 REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx)));
537 dev_dbg(vcmdq->cmdqv->dev, "%smapped\n", h);
556 FIELD_PREP(VINTF_VMID, vintf->vsmmu.vmid);
566 vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG)));
569 for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) {
570 if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) {
571 tegra241_vcmdq_map_lvcmdq(vintf->lvcmdqs[lidx]);
572 ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]);
583 static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu)
586 container_of(smmu, struct tegra241_cmdqv, smmu);
601 for (idx = 0, qidx = 0; idx < cmdqv->num_vintfs; idx++) {
602 for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) {
610 return tegra241_vintf_hw_init(cmdqv->vintfs[0], true);
617 struct arm_smmu_device *smmu = &vcmdq->cmdqv->smmu;
618 struct arm_smmu_cmdq *cmdq = &vcmdq->cmdq;
619 struct arm_smmu_queue *q = &cmdq->q;
624 snprintf(name, 16, "vcmdq%u", vcmdq->idx);
626 /* Cap queue size to SMMU's IDR1.CMDQS and ensure natural alignment */
627 regval = readl_relaxed(smmu->base + ARM_SMMU_IDR1);
628 q->llq.max_n_shift =
632 ret = arm_smmu_init_one_queue(smmu, q, vcmdq->page0,
639 q->q_base = q->base_dma & VCMDQ_ADDR;
640 q->q_base |= FIELD_PREP(VCMDQ_LOG2SIZE, q->llq.max_n_shift);
642 if (!vcmdq->vintf->hyp_own)
643 cmdq->supports_cmd = tegra241_guest_vcmdq_supports_cmd;
645 return arm_smmu_cmdq_init(smmu, cmdq);
652 vintf->lvcmdqs[lidx] = NULL;
658 struct tegra241_cmdqv *cmdqv = vintf->cmdqv;
659 u16 idx = vintf->idx;
661 vcmdq->idx = idx * cmdqv->num_lvcmdqs_per_vintf + lidx;
662 vcmdq->lidx = lidx;
663 vcmdq->cmdqv = cmdqv;
664 vcmdq->vintf = vintf;
665 vcmdq->page0 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE0(idx, lidx);
666 vcmdq->page1 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE1(idx, lidx);
668 vintf->lvcmdqs[lidx] = vcmdq;
674 struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx];
681 dev_dbg(vintf->cmdqv->dev,
683 /* Guest-owned VCMDQ is free-ed with hw_queue by iommufd core */
684 if (vcmdq->vintf->hyp_own)
691 struct tegra241_cmdqv *cmdqv = vintf->cmdqv;
698 return ERR_PTR(-ENOMEM);
709 dev_dbg(cmdqv->dev,
724 kfree(cmdqv->vintfs[idx]->lvcmdqs);
725 ida_free(&cmdqv->vintf_ids, idx);
726 cmdqv->vintfs[idx] = NULL;
736 ret = ida_alloc_max(&cmdqv->vintf_ids, max_idx, GFP_KERNEL);
741 vintf->idx = idx;
742 vintf->cmdqv = cmdqv;
743 vintf->base = cmdqv->base + TEGRA241_VINTF(idx);
745 vintf->lvcmdqs = kcalloc(cmdqv->num_lvcmdqs_per_vintf,
746 sizeof(*vintf->lvcmdqs), GFP_KERNEL);
747 if (!vintf->lvcmdqs) {
748 ida_free(&cmdqv->vintf_ids, idx);
749 return -ENOMEM;
752 cmdqv->vintfs[idx] = vintf;
760 struct tegra241_vintf *vintf = cmdqv->vintfs[idx];
766 for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++)
767 if (vintf->lvcmdqs[lidx])
770 dev_dbg(cmdqv->dev, "VINTF%u: deallocated\n", vintf->idx);
772 if (!vintf->hyp_own) {
773 mutex_destroy(&vintf->lvcmdq_mutex);
774 ida_destroy(&vintf->sids);
775 /* Guest-owned VINTF is free-ed with viommu by iommufd core */
781 static void tegra241_cmdqv_remove(struct arm_smmu_device *smmu)
784 container_of(smmu, struct tegra241_cmdqv, smmu);
788 for (idx = 0; idx < cmdqv->num_vintfs; idx++) {
789 if (cmdqv->vintfs[idx]) {
797 ida_destroy(&cmdqv->vintf_ids);
799 if (cmdqv->irq > 0)
800 free_irq(cmdqv->irq, cmdqv);
801 iounmap(cmdqv->base);
802 kfree(cmdqv->vintfs);
803 put_device(cmdqv->dev); /* smmu->impl_dev */
810 static void *tegra241_cmdqv_hw_info(struct arm_smmu_device *smmu, u32 *length,
814 container_of(smmu, struct tegra241_cmdqv, smmu);
819 return ERR_PTR(-EOPNOTSUPP);
823 return ERR_PTR(-ENOMEM);
826 info->log2vcmdqs = ilog2(cmdqv->num_lvcmdqs_per_vintf);
827 info->log2vsids = ilog2(cmdqv->num_sids_per_vintf);
828 info->version = FIELD_GET(CMDQV_VER, regval);
843 /* For in-kernel use */
847 /* For user-space use */
901 *res = *rentry->res;
918 static int tegra241_cmdqv_init_structures(struct arm_smmu_device *smmu)
921 container_of(smmu, struct tegra241_cmdqv, smmu);
928 return -ENOMEM;
930 /* Init VINTF0 for in-kernel use */
933 dev_err(cmdqv->dev, "failed to init vintf0: %d\n", ret);
938 for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) {
947 smmu->impl_ops = &tegra241_cmdqv_impl_ops;
956 __tegra241_cmdqv_probe(struct arm_smmu_device *smmu, struct resource *res,
969 static_assert(offsetof(struct tegra241_cmdqv, smmu) == 0);
971 base = ioremap(res->start, resource_size(res));
973 dev_err(smmu->dev, "failed to ioremap\n");
979 dev_info(smmu->dev, "Detected disable_cmdqv=true\n");
984 cmdqv = devm_krealloc(smmu->dev, smmu, sizeof(*cmdqv), GFP_KERNEL);
987 new_smmu = &cmdqv->smmu;
989 cmdqv->irq = irq;
990 cmdqv->base = base;
991 cmdqv->dev = smmu->impl_dev;
992 cmdqv->base_phys = res->start;
994 if (cmdqv->irq > 0) {
996 IRQF_ONESHOT, "tegra241-cmdqv",
999 dev_err(cmdqv->dev, "failed to request irq (%d): %d\n",
1000 cmdqv->irq, ret);
1006 cmdqv->num_vintfs = 1 << FIELD_GET(CMDQV_NUM_VINTF_LOG2, regval);
1007 cmdqv->num_vcmdqs = 1 << FIELD_GET(CMDQV_NUM_VCMDQ_LOG2, regval);
1008 cmdqv->num_lvcmdqs_per_vintf = cmdqv->num_vcmdqs / cmdqv->num_vintfs;
1009 cmdqv->num_sids_per_vintf =
1012 cmdqv->vintfs =
1013 kcalloc(cmdqv->num_vintfs, sizeof(*cmdqv->vintfs), GFP_KERNEL);
1014 if (!cmdqv->vintfs)
1017 ida_init(&cmdqv->vintf_ids);
1028 /* Provide init-level ops only, until tegra241_cmdqv_init_structures */
1029 new_smmu->impl_ops = &init_ops;
1034 if (cmdqv->irq > 0)
1035 free_irq(cmdqv->irq, cmdqv);
1041 struct arm_smmu_device *tegra241_cmdqv_probe(struct arm_smmu_device *smmu)
1047 if (!smmu->dev->of_node)
1048 res = tegra241_cmdqv_find_acpi_resource(smmu->impl_dev, &irq);
1052 new_smmu = __tegra241_cmdqv_probe(smmu, res, irq);
1059 dev_info(smmu->impl_dev, "Falling back to standard SMMU CMDQ\n");
1060 smmu->options &= ~ARM_SMMU_OPT_TEGRA241_CMDQV;
1061 put_device(smmu->impl_dev);
1062 return ERR_PTR(-ENODEV);
1080 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));
1082 dev_dbg(vcmdq->cmdqv->dev, "%sinited at host PA 0x%llx size 0x%lx\n",
1084 vcmdq->cmdq.q.q_base & VCMDQ_ADDR,
1085 1UL << (vcmdq->cmdq.q.q_base & VCMDQ_LOG2SIZE));
1094 mutex_lock(&vcmdq->vintf->lvcmdq_mutex);
1097 tegra241_vintf_free_lvcmdq(vcmdq->vintf, vcmdq->lidx);
1098 if (vcmdq->prev)
1099 iommufd_hw_queue_undepend(vcmdq, vcmdq->prev, core);
1100 mutex_unlock(&vcmdq->vintf->lvcmdq_mutex);
1106 struct tegra241_vintf *vintf = viommu_to_vintf(hw_queue->viommu);
1108 struct tegra241_cmdqv *cmdqv = vintf->cmdqv;
1109 struct arm_smmu_device *smmu = &cmdqv->smmu;
1115 if (hw_queue->type != IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV)
1116 return -EOPNOTSUPP;
1117 if (lidx >= cmdqv->num_lvcmdqs_per_vintf)
1118 return -EINVAL;
1120 mutex_lock(&vintf->lvcmdq_mutex);
1122 if (vintf->lvcmdqs[lidx]) {
1123 ret = -EEXIST;
1132 prev = vintf->lvcmdqs[lidx - 1];
1134 ret = -EIO;
1140 * hw_queue->length must be a power of 2, in range of
1144 readl_relaxed(smmu->base + ARM_SMMU_IDR1));
1145 if (!is_power_of_2(hw_queue->length) || hw_queue->length < 32 ||
1146 hw_queue->length > (1 << (max_n_shift + CMDQ_ENT_SZ_SHIFT))) {
1147 ret = -EINVAL;
1150 log2size = ilog2(hw_queue->length) - CMDQ_ENT_SZ_SHIFT;
1152 /* base_addr_pa must be aligned to hw_queue->length */
1154 base_addr_pa & (hw_queue->length - 1)) {
1155 ret = -EINVAL;
1169 vcmdq->prev = prev;
1175 dev_dbg(cmdqv->dev, "%sallocated\n",
1180 vcmdq->cmdq.q.q_base = base_addr_pa & VCMDQ_ADDR;
1181 vcmdq->cmdq.q.q_base |= log2size;
1187 hw_queue->destroy = &tegra241_vintf_destroy_lvcmdq_user;
1188 mutex_unlock(&vintf->lvcmdq_mutex);
1195 if (vcmdq->prev)
1196 iommufd_hw_queue_undepend(vcmdq, vcmdq->prev, core);
1198 mutex_unlock(&vintf->lvcmdq_mutex);
1206 if (vintf->mmap_offset)
1207 iommufd_viommu_destroy_mmap(&vintf->vsmmu.core,
1208 vintf->mmap_offset);
1209 tegra241_cmdqv_remove_vintf(vintf->cmdqv, vintf->idx);
1215 struct tegra241_vintf *vintf = vsid->vintf;
1217 writel(0, REG_VINTF(vintf, SID_MATCH(vsid->idx)));
1218 writel(0, REG_VINTF(vintf, SID_REPLACE(vsid->idx)));
1219 ida_free(&vintf->sids, vsid->idx);
1220 dev_dbg(vintf->cmdqv->dev,
1221 "VINTF%u: deallocated SID_REPLACE%d for pSID=%x\n", vintf->idx,
1222 vsid->idx, vsid->sid);
1229 struct tegra241_vintf *vintf = viommu_to_vintf(vdev->viommu);
1231 struct arm_smmu_stream *stream = &master->streams[0];
1232 u64 virt_sid = vdev->virt_id;
1236 return -EINVAL;
1238 WARN_ON_ONCE(master->num_streams != 1);
1241 sidx = ida_alloc_max(&vintf->sids, vintf->cmdqv->num_sids_per_vintf - 1,
1246 writel(stream->id, REG_VINTF(vintf, SID_REPLACE(sidx)));
1248 dev_dbg(vintf->cmdqv->dev,
1250 vintf->idx, sidx, stream->id, (u32)virt_sid);
1252 vsid->idx = sidx;
1253 vsid->vintf = vintf;
1254 vsid->sid = stream->id;
1256 vdev->destroy = &tegra241_vintf_destroy_vsid;
1263 /* Non-accelerated commands will be still handled by the kernel */
1276 container_of(vsmmu->smmu, struct tegra241_cmdqv, smmu);
1277 struct tegra241_vintf *vintf = viommu_to_vintf(&vsmmu->core);
1286 if (WARN_ON(vsmmu->core.type != IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV))
1287 return -EOPNOTSUPP;
1290 return -EINVAL;
1298 ret = tegra241_cmdqv_init_vintf(cmdqv, cmdqv->num_vintfs - 1, vintf);
1300 dev_err(cmdqv->dev, "no more available vintf\n");
1305 * Initialize the user-owned VINTF without a LVCMDQ, as it cannot pre-
1307 * It is different than the kernel-owned VINTF0, which had pre-assigned
1308 * and pre-allocated global VCMDQs that would be mapped to the LVCMDQs
1315 page0_base = cmdqv->base_phys + TEGRA241_VINTFi_PAGE0(vintf->idx);
1316 ret = iommufd_viommu_alloc_mmap(&vintf->vsmmu.core, page0_base, SZ_64K,
1317 &vintf->mmap_offset);
1322 data.out_vintf_mmap_offset = vintf->mmap_offset;
1329 ida_init(&vintf->sids);
1330 mutex_init(&vintf->lvcmdq_mutex);
1332 dev_dbg(cmdqv->dev, "VINTF%u: allocated with vmid (%d)\n", vintf->idx,
1333 vintf->vsmmu.vmid);
1335 vsmmu->core.ops = &tegra241_cmdqv_viommu_ops;
1339 iommufd_viommu_destroy_mmap(&vintf->vsmmu.core, vintf->mmap_offset);
1343 tegra241_cmdqv_deinit_vintf(cmdqv, vintf->idx);