Home
last modified time | relevance | path

Searched +full:apb +full:- +full:base (Results 1 – 25 of 93) sorted by relevance

1234

/linux/Documentation/devicetree/bindings/phy/
H A Dintel,keembay-phy-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
32 - mediatek,mt2701-smi-common
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
36 /* info located in APB */
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
74 struct regmap *apb; member
81 /* Per-slot PERST# */
86 /* Per-slot clkreq */
99 /* PHY info located in APB */
126 void __iomem *base; member
[all …]
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/drivers/clk/mmp/
H A Dclk-apbc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp APB clock operation source file
17 /* Common APB clock register bit definitions */
18 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
26 void __iomem *base; member
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
[all …]
/linux/arch/arc/boot/dts/
H A Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
[all …]
/linux/drivers/clocksource/
H A Ddw_apb_timer_of.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modified from mach-picoxcell/time.c
18 void __iomem **base, u32 *rate) in timer_get_base_and_rate() argument
25 *base = of_iomap(np, 0); in timer_get_base_and_rate()
27 if (!*base) in timer_get_base_and_rate()
50 if (!of_property_read_u32(np, "clock-freq", rate) || in timer_get_base_and_rate()
51 !of_property_read_u32(np, "clock-frequency", rate)) in timer_get_base_and_rate()
66 ret = -EINVAL; in timer_get_base_and_rate()
81 iounmap(*base); in timer_get_base_and_rate()
100 ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq, in add_clockevent()
[all …]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
35 /* USS APB slave registers */
76 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_CLK_SET, in keembay_usb_clocks_on()
79 dev_err(priv->dev, "error clock set: %d\n", ret); in keembay_usb_clocks_on()
83 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_RST_SET, in keembay_usb_clocks_on()
86 dev_err(priv->dev, "error reset set: %d\n", ret); in keembay_usb_clocks_on()
90 ret = regmap_update_bits(priv->regmap_slv, in keembay_usb_clocks_on()
95 dev_err(priv->dev, "error iddq disable: %d\n", ret); in keembay_usb_clocks_on()
102 ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG0, in keembay_usb_clocks_on()
106 dev_err(priv->dev, "error ref clock select: %d\n", ret); in keembay_usb_clocks_on()
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
[all …]
H A Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
[all …]
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
31 * intermediate DW APB GPIO blocks (mainly for debouncing) in axs10x_enable_gpio_intc_wire()
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
[all …]
/linux/drivers/pmdomain/imx/
H A Dimx8mp-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
19 #include <dt-bindings/power/imx8mp-power.h>
104 regmap_update_bits(clk->regmap, GPR_REG2, in clk_hsio_pll_prepare()
110 /* de-assert PLL reset */ in clk_hsio_pll_prepare()
111 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); in clk_hsio_pll_prepare()
114 regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); in clk_hsio_pll_prepare()
116 return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, in clk_hsio_pll_prepare()
124 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); in clk_hsio_pll_unprepare()
131 return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); in clk_hsio_pll_is_prepared()
[all …]
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
93 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
95 pm_runtime_put_noidle(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
[all …]
/linux/sound/soc/starfive/
H A Djh7110_pwmdac.c1 // SPDX-License-Identifier: GPL-2.0
3 * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver
5 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
90 void __iomem *base; member
115 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_enable()
121 jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); in jh7110_pwmdac_set_enable()
128 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_shift()
129 if (dev->cfg.shift == PWMDAC_SHIFT_8) in jh7110_pwmdac_set_shift()
131 else if (dev->cfg.shift == PWMDAC_SHIFT_10) in jh7110_pwmdac_set_shift()
134 jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); in jh7110_pwmdac_set_shift()
[all …]
/linux/drivers/clk/
H A Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
77 * struct gemini_reset - gemini reset controller
90 { 1, "security-gate", "secdiv", 0 },
[all …]
H A Dclk-moxart.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
18 void __iomem *base; in moxart_of_pll_clk_init() local
22 const char *name = node->name; in moxart_of_pll_clk_init()
25 of_property_read_string(node, "clock-output-names", &name); in moxart_of_pll_clk_init()
28 base = of_iomap(node, 0); in moxart_of_pll_clk_init()
29 if (!base) { in moxart_of_pll_clk_init()
34 mul = readl(base + 0x30) >> 3 & 0x3f; in moxart_of_pll_clk_init()
35 iounmap(base); in moxart_of_pll_clk_init()
52 CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
47 * the base (2x, 4x and 8x), and one variable divider (the one true
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
87 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
103 .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
[all …]
/linux/arch/sparc/kernel/
H A Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <asm/apb.h>
115 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
116 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
119 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry …
138 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
140 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
141 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
142 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
143 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
[all …]
/linux/drivers/watchdog/
H A Dstarfive-wdt.c1 // SPDX-License-Identifier: GPL-2.0
103 void __iomem *base; member
150 ret = clk_prepare_enable(wdt->apb_clk); in starfive_wdt_enable_clock()
152 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n"); in starfive_wdt_enable_clock()
154 ret = clk_prepare_enable(wdt->core_clk); in starfive_wdt_enable_clock()
156 clk_disable_unprepare(wdt->apb_clk); in starfive_wdt_enable_clock()
157 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n"); in starfive_wdt_enable_clock()
165 clk_disable_unprepare(wdt->core_clk); in starfive_wdt_disable_clock()
166 clk_disable_unprepare(wdt->apb_clk); in starfive_wdt_disable_clock()
171 struct device *dev = wdt->wdd.parent; in starfive_wdt_get_clock()
[all …]
/linux/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
28 - description: Module Clock
[all …]
/linux/drivers/pwm/
H A Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
38 void __iomem *base; member
66 u64 prescaled_ns = (u64)pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
67 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
73 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
77 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
81 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
83 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
85 state->period = DIV_U64_ROUND_UP(tmp, clk_rate); in rockchip_pwm_get_state()
87 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear300.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear300-pinmux";
31 compatible = "st,spear600-fsmc-nand";
32 #address-cells = <1>;
33 #size-cells = <1>;
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
[all …]

1234