Lines Matching +full:apb +full:- +full:base

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 	#address-cells = <2>;
16 	#size-cells = <2>;
19 		compatible = "simple-bus";
20 		#address-cells = <1>;
21 		#size-cells = <1>;
26 			#clock-cells = <0>;
27 			compatible = "fixed-clock";
28 			clock-frequency = <750000000>;
31 		input_clk: input-clk {
32 			#clock-cells = <0>;
33 			compatible = "fixed-clock";
34 			clock-frequency = <33333333>;
37 		core_intc: arc700-intc@cpu {
38 			compatible = "snps,arc700-intc";
39 			interrupt-controller;
40 			#interrupt-cells = <1>;
47 		dw-apb-gpio@2000 {
48 			compatible = "snps,dw-apb-gpio";
50 			#address-cells = <1>;
51 			#size-cells = <0>;
53 			ictl_intc: gpio-controller@0 {
54 				compatible = "snps,dw-apb-gpio-port";
55 				gpio-controller;
56 				#gpio-cells = <2>;
57 				snps,nr-gpios = <30>;
59 				interrupt-controller;
60 				#interrupt-cells = <2>;
61 				interrupt-parent = <&core_intc>;
66 		debug_uart: dw-apb-uart@5000 {
67 			compatible = "snps,dw-apb-uart";
69 			clock-frequency = <33333000>;
70 			interrupt-parent = <&ictl_intc>;
73 			reg-shift = <2>;
74 			reg-io-width = <4>;
78 			compatible = "snps,arc700-pct";
83 	 * This INTC is actually connected to DW APB GPIO
94 	mb_intc: interrupt-controller@e0012000 {
95 		#interrupt-cells = <1>;
96 		compatible = "snps,dw-apb-ictl";
98 		interrupt-controller;
99 		interrupt-parent = <&core_intc>;
106 		reg = <0x0 0x80000000 0x0 0x1b000000>;	/* (512 - 32) MiB */
109 	reserved-memory {
110 		#address-cells = <2>;
111 		#size-cells = <2>;
116 		 * no strict requirement for a frame-buffer to be in any
118 		 * base board's DT node for ARC PGU as for ARc HS38.
121 			compatible = "shared-dma-pool";
123 			no-map;