Lines Matching +full:apb +full:- +full:base
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
19 - renesas,r8a774b1-pcie-ep # RZ/G2N
20 - renesas,r8a774c0-pcie-ep # RZ/G2E
21 - renesas,r8a774e1-pcie-ep # RZ/G2H
22 - renesas,r8a7795-pcie-ep # R-Car H3
23 - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
28 reg-names:
30 - const: apb-base
31 - const: memory0
32 - const: memory1
33 - const: memory2
34 - const: memory3
40 power-domains:
49 clock-names:
51 - const: pcie
53 max-functions:
58 - compatible
59 - reg
60 - reg-names
61 - interrupts
62 - resets
63 - power-domains
64 - clocks
65 - clock-names
66 - max-functions
71 - |
72 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 #include <dt-bindings/power/r8a774c0-sysc.h>
76 pcie0_ep: pcie-ep@fe000000 {
77 compatible = "renesas,r8a774c0-pcie-ep",
78 "renesas,rcar-gen3-pcie-ep";
84 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
89 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
91 clock-names = "pcie";
92 max-functions = /bits/ 8 <1>;