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/linux/drivers/staging/fbtft/
H A Dfb_upd161704.c47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ in init_display()
49 write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */ in init_display()
50 write_reg(par, 0x0063, 0x0022); /* adjustment V34 positive polarity */ in init_display()
52 write_reg(par, 0x0064, 0x0027); /* adjustment V31 negative polarity */ in init_display()
54 write_reg(par, 0x0065, 0x0014); /* adjustment V61 negative polarity */ in init_display()
56 write_reg(par, 0x0066, 0x0010); /* adjustment V61 negative polarity */ in init_display()
/linux/Documentation/networking/
H A Dila.rst137 adjustment can be precomputed and saved with the mapping.
139 Note that the checksum neutral adjustment affects the low order sixteen
184 adjustment value are not present so an identifier is considered an
193 The checksum neutral adjustment may be configured to always be
195 checksum adjustment is in the low order 16 bits. The identifier is
201 | | Checksum-neutral adjustment |
210 | | Checksum-neutral adjustment |
215 configuration. The checksum neutral adjustment may automatically
221 | | Checksum-neutral adjustment |
230 | | Checksum-neutral adjustment |
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_ptp.c16 /* 16 nano second time quantas to wait before making a Drift adjustment */
18 /* Nano seconds to add/subtract when making a Drift adjustment */
20 /* Add/subtract the Adjustment_Value when making a Drift adjustment */
248 * FW/HW accepts the adjustment value in terms of 3 parameters:
249 * Drift period - adjustment happens once in certain number of nano seconds.
251 * Drift direction - add or subtract the adjustment value.
252 * The routine translates ppb into the adjustment triplet in an optimal manner.
270 /* Adjustment value is up to +/-7ns, find an optimal value in in qed_ptp_hw_adjfreq()
/linux/drivers/ptp/
H A Dptp_dfl_tod.c75 * A fine ToD HW clock offset adjustment. To perform the fine offset adjustment, the
89 /* Wait for present offset adjustment update to complete */ in fine_adjust_tod_clock()
95 * A coarse ToD HW clock offset adjustment. The coarse time adjustment performs by
189 * adjustment in nanoseconds scale. This depends on the current in dfl_tod_adjust_time()
/linux/Documentation/devicetree/bindings/sound/
H A Dst,sta350.txt42 - st,thermal-warning-adjustment:
43 If present, thermal warning adjustment is enabled.
63 - st,overcurrent-warning-adjustment:
64 If present, overcurrent warning adjustment is enabled.
/linux/net/ipv6/netfilter/
H A Dip6t_NPT.c35 npt->adjustment = ~csum_fold(csum_sub(src_sum, dst_sum)); in ip6t_npt_checkentry()
72 csum_unfold(npt->adjustment))); in ip6t_npt_map_pfx()
151 .usersize = offsetof(struct ip6t_npt_tginfo, adjustment),
163 .usersize = offsetof(struct ip6t_npt_tginfo, adjustment),
/linux/drivers/md/persistent-data/
H A Ddm-space-map-metadata.c308 unsigned int adjustment = 0; in sm_metadata_get_count() local
324 adjustment++; in sm_metadata_get_count()
328 adjustment--; in sm_metadata_get_count()
337 *result += adjustment; in sm_metadata_get_count()
345 int r, adjustment = 0; in sm_metadata_count_is_more_than_one() local
365 adjustment++; in sm_metadata_count_is_more_than_one()
369 adjustment--; in sm_metadata_count_is_more_than_one()
374 if (adjustment > 1) { in sm_metadata_count_is_more_than_one()
389 *result = rc + adjustment > 1; in sm_metadata_count_is_more_than_one()
/linux/sound/soc/sti/
H A Duniperif_player.c157 int adjustment = player->clk_adj; in uni_player_clk_set_rate() local
170 * a - adjustment in ppm (parts per milion) in uni_player_clk_set_rate()
174 if (adjustment < 0) { in uni_player_clk_set_rate()
177 adjustment = -adjustment; in uni_player_clk_set_rate()
183 (uint64_t)adjustment + 500000, 1000000); in uni_player_clk_set_rate()
200 * Using ALSA's adjustment control, we can modify the rate to be up in uni_player_clk_set_rate()
207 adjustment = -1; in uni_player_clk_set_rate()
209 adjustment = 1; in uni_player_clk_set_rate()
212 adjustment *= (int)div64_u64((uint64_t)delta * 1000000 + rate / 2, in uni_player_clk_set_rate()
214 player->clk_adj = adjustment; in uni_player_clk_set_rate()
[all …]
/linux/include/uapi/linux/
H A Domap3isp.h542 * struct omap3isp_prev_blkadj - Black Level Adjustment
543 * @red: Black level offset adjustment for Red in 2's complement format
544 * @green: Black level offset adjustment for Green in 2's complement format
545 * @blue: Black level offset adjustment for Blue in 2's complement format
548 /*Black level offset adjustment for Red in 2's complement format */
550 /*Black level offset adjustment for Green in 2's complement format */
552 /* Black level offset adjustment for Blue in 2's complement format */
648 * @blkadj: Pointer to structure for Black Adjustment.
/linux/Documentation/devicetree/bindings/net/
H A Damlogic,meson-dwmac.yaml50 - description: The clock which drives the timing adjustment logic
58 - const: timing-adjustment
174 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100-starfive-visionfive-v1.dts27 * manual adjustment of the RX internal delay to work properly. The default
31 * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
/linux/kernel/locking/
H A Drwsem.c414 long oldcount, woken = 0, adjustment = 0; in rwsem_mark_wake() local
455 adjustment = RWSEM_READER_BIAS; in rwsem_mark_wake()
456 oldcount = atomic_long_fetch_add(adjustment, &sem->count); in rwsem_mark_wake()
465 adjustment -= RWSEM_FLAG_HANDOFF; in rwsem_mark_wake()
471 atomic_long_add(-adjustment, &sem->count); in rwsem_mark_wake()
522 adjustment = woken * RWSEM_READER_BIAS - adjustment; in rwsem_mark_wake()
531 adjustment -= RWSEM_FLAG_WAITERS; in rwsem_mark_wake()
533 adjustment -= RWSEM_FLAG_HANDOFF; in rwsem_mark_wake()
540 adjustment -= RWSEM_FLAG_HANDOFF; in rwsem_mark_wake()
543 if (adjustment) in rwsem_mark_wake()
[all …]
/linux/Documentation/driver-api/
H A Ddpll.rst176 Phase offset measurement and adjustment
185 If pin phase adjustment is supported, minimal and maximal values that pin
194 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
195 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
197 adjustment on parent dpll device
329 adjustment
331 adjustment
333 adjustment on parent device
358 adjustment on parent device
/linux/tools/testing/selftests/timers/
H A Dadjtick.c1 /* adjtimex() tick adjustment test
151 * with the adjustment, resulting in > 10ppm error during in check_tick_adj()
152 * a 10% adjustment. 100ppm also gives us more breathing in check_tick_adj()
H A Dchange_skew.c65 /* Make sure there's no offset adjustment going on */ in main()
76 printf("Using %i ppm adjustment\n", ppm[i]); in main()
/linux/include/drm/display/
H A Ddrm_dsc.h114 * Offset to bits/group used by RC to determine QP adjustment
119 * Offset to bits/group used by RC to determine QP adjustment
267 * Offset adjustment for second line in Native 4:2:0 mode
451 * flatness QP adjustment is made.
458 * the flatness adjustment is made.
531 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
/linux/drivers/media/tuners/
H A Dqt1010_priv.h32 11 f1 ? maybe device specified adjustment
33 12 11 ? maybe device specified adjustment
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1663 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1664 * registers. The atomic adjustment won't be completed until the driver issues
1715 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1717 * @adj: adjustment in nanoseconds
1719 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1720 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1732 /* The port clock supports adjustment of the sub-nanosecond portion of in ice_ptp_prep_phy_adj_eth56g()
1733 * the clock (lowest 32 bits). We shift the provided adjustment in in ice_ptp_prep_phy_adj_eth56g()
1734 * nanoseconds by 32 to calculate the appropriate adjustment to program in ice_ptp_prep_phy_adj_eth56g()
1751 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
[all …]
/linux/drivers/clk/
H A Dclk-si544.c54 /* Range and interpretation of the adjustment value */
250 /* Reset the frequency adjustment */ in si544_calc_muldiv()
283 * The clock adjustment is much smaller than 1 Hz, round to the in si544_calc_rate()
354 /* Try using the frequency adjustment feature for a <= 950ppm change */ in si544_set_rate()
367 /* Too big for the delta adjustment, need to reprogram */ in si544_set_rate()
/linux/drivers/gpu/drm/amd/include/
H A Damd_shared.h187 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
188 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
189 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
199 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
200 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
/linux/drivers/net/phy/qcom/
H A Dqca83xx.c128 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. in qca8327_config_init()
140 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ in qca83xx_link_change_notify()
147 /* Reset DAC Amplitude adjustment */ in qca83xx_link_change_notify()
/linux/drivers/macintosh/
H A Dwindfarm_pid.h25 * but could be implemented (with necessary adjustment of the history
59 * but could be implemented (with necessary adjustment of the history
/linux/arch/x86/kernel/
H A Dtsc_sync.c127 * adjustment value. This value might change later via the sync in tsc_sanitize_first_cpu()
226 * value on this newly upcoming CPU differs from the adjustment in tsc_store_and_check_tsc_adjust()
506 * Add the result to the previous adjustment value. in check_tsc_sync_target()
508 * The adjustment value is slightly off by the overhead of the in check_tsc_sync_target()
513 * value is used. In the worst case the adjustment needs to go in check_tsc_sync_target()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8183-pinctrl.yaml123 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
171 cycle when asserted (high pulse width adjustment). Valid arguments
178 when asserted (high pulse width adjustment). Valid arguments are
/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dclk.h100 int astate; /* perfmon adjustment (base) */
101 int dstate; /* display adjustment (min+) */

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