| /linux/Documentation/devicetree/bindings/access-controllers/ |
| H A D | access-controllers.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Domain Access Controllers
10 - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
13 Common access controllers properties
15 Access controllers are in charge of stating which of the hardware blocks under
18 or a group of hardware blocks. An access controller's domain is the set of
19 resources covered by the access controller.
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
16 layouts for the controllers share many similarities, but also some
25 a) Security registers, which allow configuration of allowed access to the
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| /linux/drivers/bus/ |
| H A D | stm32_firewall.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
40 return -EINVAL; in stm32_firewall_get_firewall()
43 of_for_each_phandle(&it, err, np, "access-controllers", "#access-controller-cells", 0) { in stm32_firewall_get_firewall()
50 pr_err("Unable to get access-controllers property for node %s\n, err: %d", in stm32_firewall_get_firewall()
51 np->full_name, err); in stm32_firewall_get_firewall()
57 pr_err("Too many firewall controllers"); in stm32_firewall_get_firewall()
59 return -EINVAL; in stm32_firewall_get_firewall()
68 if (ctrl->dev->of_node->phandle == it.phandle) { in stm32_firewall_get_firewall()
78 pr_err("No firewall controller registered for %s\n", np->full_name); in stm32_firewall_get_firewall()
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| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
65 access.
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | st,stm32-etzpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 devices with programmable-security attributes (securable resources).
14 - Gatien Chevallier <gatien.chevallier@foss.st.com>
20 const: st,stm32-etzpc
22 - compatible
27 - const: st,stm32-etzpc
28 - const: simple-bus
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| H A D | st,stm32mp25-rifsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <gatien.chevallier@foss.st.com>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
25 Alternatively, the RISUP logic controlling the device port access to a
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| /linux/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
26 2-3. [Un]populated Notification
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| /linux/arch/arm64/boot/dts/st/ |
| H A D | stm32mp255.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
10 compatible = "st,stm32mp25-vdec";
14 access-controllers = <&rifsc 89>;
19 compatible = "st,stm32mp25-venc";
23 access-controllers = <&rifsc 90>;
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | intel,ixp4xx-expansion-bus-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
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| H A D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
19 Select. The FMC2 performs only one access at a time to an external device.
22 - Christophe Kerello <christophe.kerello@foss.st.com>
27 - st,stm32mp1-fmc2-ebi
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| /linux/Documentation/gpu/ |
| H A D | tegra.rst | 11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
56 --------------------------
58 .. kernel-doc:: drivers/gpu/host1x/syncpt.c
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| /linux/Documentation/core-api/ |
| H A D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
8 Basically all FireWire controllers which are in use today are compliant
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
25 With most FireWire controllers, memory access is limited to the low 4 GB
28 hardware such as x86, x86-64 and PowerPC.
30 At least LSI FW643e and FW643e2 controllers are known to support access to
34 Together with a early initialization of the OHCI-1394 controller for debugging,
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp153.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
12 compatible = "arm,cortex-a7";
13 clock-frequency = <650000000>;
19 arm-pmu {
22 interrupt-affinity = <&cpu0>, <&cpu1>;
37 reg-names = "m_can", "message_ram";
40 interrupt-names = "int0", "int1";
42 clock-names = "hclk", "cclk";
43 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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|
| H A D | stm32mp133.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
14 reg-names = "m_can", "message_ram";
17 interrupt-names = "int0", "int1";
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
27 reg-names = "m_can", "message_ram";
30 interrupt-names = "int0", "int1";
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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| /linux/include/sound/ac97/ |
| H A D | controller.h | 1 /* SPDX-License-Identifier: GPL-2.0
18 * struct ac97_controller - The AC97 controller of the AC-Link
20 * @controllers: linked list of all existing controllers.
21 * @adap: the shell device ac97-%d, ie. ac97 adapter
29 * controllers themselves, excepting for using @dev.
33 struct list_head controllers; member
43 * struct ac97_controller_ops - The AC97 operations
44 * @reset: Cold reset of the AC97 AC-Link.
45 * @warm_reset: Warm reset of the AC97 AC-Link.
51 * access functions. Amongst these, all but the last 2 are mandatory.
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| /linux/drivers/usb/usbip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
10 machines direct access to USB devices. It provides the
17 be called usbip-core.
29 module will be called vhci-hcd.
42 int "Number of USB/IP virtual host controllers"
49 virtual host controllers as if adding physical host
50 controllers.
60 module will be called usbip-host.
71 module will be called usbip-vudc.
|
| /linux/drivers/usb/gadget/udc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
20 # The order here is alphabetical, except that integrated controllers go
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-orion.txt | 4 - compatible : should be on of the following:
5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
11 - reg : offset and length of the register set for the device.
13 the SPI direct access mode that some of the Marvell SoCs support
14 additionally to the normal indirect access (PIO) mode. The values
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| /linux/drivers/scsi/aic7xxx/ |
| H A D | aic7xxx_osm_pci.c | 2 * Linux driver attachment glue for PCI based controllers.
4 * Copyright (c) 2000-2001 Adaptec Inc.
18 * 3. Neither the names of the above-listed copyright holders nor the names
50 /* aic7850 based controllers */
52 /* aic7860 based controllers */
58 /* aic7870 based controllers */
65 /* aic7880 based controllers */
75 /* aic7890 based controllers */
83 /* aic7890 based controllers */
91 /* aic7892 based controllers */
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| /linux/drivers/iommu/ |
| H A D | exynos-iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
25 #include "iommu-pages.h"
40 #define SECT_MASK (~(SECT_SIZE - 1))
41 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
42 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
57 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
60 * All SYSMMU controllers in the system support the address spaces of the same
64 static short PG_ENT_SHIFT = -1;
70 ((0 << 15) | (0 << 10)), /* no access */
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| /linux/drivers/hid/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
22 most commonly used to refer to the USB-HID specification, but other
27 removed from the HID bus by the transport-layer drivers, such as
58 to work on raw hid events when they want to, and avoid using transport-specific
64 tristate "User-space I/O driver support for HID subsystem"
67 Say Y here if you want to provide HID I/O Drivers from user-space.
68 This allows to write I/O drivers in user-space and feed the data from
71 user-space device.
73 This driver cannot be used to parse HID-reports in user-space and write
74 special HID-drivers. You should use hidraw for that.
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| /linux/drivers/firewire/ |
| H A D | init_ohci1394_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
5 * Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de>
7 * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
9 * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
10 * - reset and initialize them and make them join the IEEE1394 bus and
11 * - enable physical DMA on them to allow remote debugging
14 * during boot, all OHCI1394 controllers may be claimed by the firewire
18 * be sure that the stack enables it and (re-)attach after the bus reset
28 #include <asm/pci-direct.h> /* for direct PCI config space access */
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| /linux/Documentation/admin-guide/gpio/ |
| H A D | gpio-aggregator.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
11 -----------------------------
13 GPIO controllers are exported to userspace using /dev/gpiochip* character
14 devices. Access control to these devices is provided by standard UNIX file
15 system permissions, on an all-or-nothing basis: either a GPIO controller is
18 The GPIO Aggregator provides access control for a set of one or more GPIOs, by
25 Aggregated GPIO controllers are instantiated and destroyed by writing to
26 write-only attribute files in sysfs.
28 /sys/bus/platform/drivers/gpio-aggregator/
35 .. code-block:: none
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| /linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 useful mostly on embedded systems. These could be controllers
13 access to attached peripherals through memory bus.
23 DDR SDRAM controllers.
42 Used to configure the EBI (external bus interface) when the device-
51 This driver provides access to the DPFE interface of Broadcom
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
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| /linux/Documentation/devicetree/bindings/fsi/ |
| H A D | fsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/fsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eddie James <eajames@linux.ibm.com>
14 FSI bus is connected to a CFAM (Common FRU Access Macro) which contains
15 various engines such as I2C controllers, SPI controllers, etc.
18 "#address-cells":
21 "#size-cells":
24 '#interrupt-cells':
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