Zynq\-7000 (full) in projects: linux - OpenGrok search results

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Searched +full:zynq +full:- +full:7000 (Results 1 – 23 of 23) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/xilinx/
H A D	xilinx.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx Zynq Platforms 10 - Michal Simek <michal.simek@amd.com> 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC 20 - items: 21 - enum: 22 - adapteva,parallella 23 - digilent,zynq-zybo [all …]`
/linux/arch/arm/boot/dts/xilinx/
H A D	zynq-zed.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; 26 stdout-path = "serial0:115200n8"; 30 compatible = "usb-nop-xceiv"; 31 #phy-cells = <0>; 36 ps-clk-frequency = <33333333>; 41 phy-mode = "rgmii-id"; [all …]`
H A D	zynq-zybo-z7.dts	`1 // SPDX-License-Identifier: GPL-2.0+ 2 /dts-v1/; 3 #include "zynq-7000.dtsi" 4 #include <dt-bindings/gpio/gpio.h> 8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; 22 stdout-path = "serial0:115200n8"; 25 gpio-leds { 26 compatible = "gpio-leds"; 28 led-ld4 { 29 label = "zynq-zybo-z7:green:ld4"; [all …]`
H A D	zynq-microzed.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 /include/ "zynq-7000.dtsi" 11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; 25 stdout-path = "serial0:115200n8"; 29 compatible = "usb-nop-xceiv"; 30 #phy-cells = <0>; 35 ps-clk-frequency = <33333333>; 40 phy-mode = "rgmii-id"; [all …]`
H A D	zynq-zybo.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; 26 stdout-path = "serial0:115200n8"; 30 #phy-cells = <0>; 31 compatible = "usb-nop-xceiv"; 32 reset-gpios = <&gpio0 46 1>; 37 ps-clk-frequency = <50000000>; [all …]`
H A D	zynq-zc770-xm011.dts	`1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; 22 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 42 clock-frequency = <400000>; 52 num-cs = <4>; [all …]`
H A D	zynq-zc770-xm012.dts	`1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 38 clock-frequency = <400000>; 48 clock-frequency = <400000>; 58 num-cs = <4>; 59 is-decoded-cs = <0>;`
H A D	zynq-cc108.dts	`1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2007-2018 Xilinx, Inc. 6 * (C) Copyright 2007-2013 Michal Simek 7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 11 /dts-v1/; 12 /include/ "zynq-7000.dtsi" 16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; 25 stdout-path = "serial0:115200n8"; 34 compatible = "usb-nop-xceiv"; 35 #phy-cells = <0>; [all …]`
H A D	zynq-zc770-xm013.dts	`1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 38 phy-mode = "rgmii-id"; 39 phy-handle = <&ethernet_phy>; 41 ethernet_phy: ethernet-phy@7 { 43 device_type = "ethernet-phy"; 49 clock-frequency = <400000>; [all …]`
H A D	zynq-parallella.dts	`1 // SPDX-License-Identifier: GPL-2.0 5 * Derived from zynq-zed.dts: 11 /dts-v1/; 12 /include/ "zynq-7000.dtsi" 16 compatible = "adapteva,parallella", "xlnx,zynq-7000"; 30 stdout-path = "serial0:115200n8"; 35 fclk-enable = <0xf>; 36 ps-clk-frequency = <33333333>; 41 phy-mode = "rgmii-id"; 42 phy-handle = <&ethernet_phy>; [all …]`
H A D	zynq-zc770-xm010.dts	`1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 32 compatible = "usb-nop-xceiv"; 33 #phy-cells = <0>; 43 phy-mode = "rgmii-id"; 44 phy-handle = <&ethernet_phy>; [all …]`
H A D	zynq-zturn-common.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 6 * Based on zynq-zed.dts which is: 7 * Copyright (C) 2011 - 2014 Xilinx 12 /dts-v1/; 13 /include/ "zynq-7000.dtsi" 16 compatible = "xlnx,zynq-7000"; 31 stdout-path = "serial0:115200n8"; 34 gpio-leds { 35 compatible = "gpio-leds"; 36 usr-led1 { [all …]`
H A D	zynq-zturn-v5.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 /dts-v1/; 4 /include/ "zynq-zturn-common.dtsi" 7 model = "Zynq Z-Turn MYIR Board V5"; 8 compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; 12 ethernet_phy: ethernet-phy@0 {`
H A D	zynq-zturn.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 /dts-v1/; 4 /include/ "zynq-zturn-common.dtsi" 7 model = "Zynq Z-Turn MYIR Board"; 8 compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; 12 ethernet_phy: ethernet-phy@0 {`
H A D	zynq-ebaz4205.dts	`1 // SPDX-License-Identifier: GPL-2.0 5 /dts-v1/; 6 /include/ "zynq-7000.dtsi" 10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 28 ps-clk-frequency = <33333333>; 29 fclk-enable = <8>; 34 phy-mode = "mii"; 35 phy-handle = <&phy>; 38 assigned-clocks = <&clkc 18>; [all …]`
H A D	zynq-zc706.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; 27 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 37 ps-clk-frequency = <33333333>; 42 phy-mode = "rgmii-id"; [all …]`
H A D	zynq-zc702.dts	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 8 #include <dt-bindings/gpio/gpio.h> 12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; 28 stdout-path = "serial0:115200n8"; 31 gpio-keys { 32 compatible = "gpio-keys"; 34 switch-14 { [all …]`
H A D	zynq-7000.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 12 #address-cells = <1>; 13 #size-cells = <0>; 16 compatible = "arm,cortex-a9"; 20 clock-latency = <1000>; 21 cpu0-supply = <&regulator_vccpint>; [all …]`
/linux/Documentation/devicetree/bindings/net/can/
H A D	ctu,ctucanfd.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: CTU CAN FD Open-source IP Core 10 Open-source CAN FD IP core developed at the Czech Technical University in Prague 16 Integration in Xilinx Zynq SoC based system together with 18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top 21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-… 24 - Pavel Pisa <pisa@cmp.felk.cvut.cz> 25 - Ondrej Ille <ondrej.ille@gmail.com> [all …]
/linux/Documentation/devicetree/bindings/clock/
H A D	zynq-7000.txt	1 Device Tree Clock bindings for the Zynq 7000 EPP 3 The Zynq EPP has several different clk providers, each with there own bindings. 7 See Chapter 25 of Zynq TRM for more information about Zynq clocks. 10 The clock controller is a logical abstraction of Zynq's clock tree. It reads 15 - #clock-cells : Must be 1 16 - compatible : "xlnx,ps7-clkc" 17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 > 18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ 19 (usually 33 MHz oscillators are used for Zynq platforms) 20 - clock-output-names : List of strings used to name the clock outputs. Shall be [all …]
/linux/arch/arm/mach-zynq/
H A D	common.c	`1 // SPDX-License-Identifier: GPL-2.0-only 15 #include <linux/clk/zynq.h> 24 #include <linux/irqchip/arm-gic.h> 32 #include <asm/mach-types.h> 36 #include <asm/hardware/cache-l2x0.h> 47 * zynq_memory_init - Initialize special memory 59 .name = "cpuidle-zynq", 63 * zynq_get_revision - Get Zynq silicon revision 65 * Return: Silicon version or -1 otherwise 73 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0"); in zynq_get_revision() [all …]`
/linux/Documentation/devicetree/bindings/display/
H A D	xylon,logicvc-display.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. 20 synthesis time. As a result, many of the device-tree bindings are meant to 24 Layers are declared in the "layers" sub-node and have dedicated configuration. 32 - xylon,logicvc-3.02.a-display 33 - xylon,logicvc-4.01.a-display [all …]
/linux/drivers/video/fbdev/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0-only 14 a well-defined interface, so the software doesn't need to know 15 anything about the low-level (hardware register) stuff. 21 On several non-X86 architectures, the frame buffer device is the 29 and the Framebuffer-HOWTO at 30 <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more 40 are compiling a kernel for a non-x86 architecture. 46 device-aware may cause unexpected results. If unsure, say N. 57 Common utility functions useful to fbdev drivers of VGA-based 82 If you have a PCI-based system, this enables support for these [all …]