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/freebsd/crypto/openssl/crypto/chacha/
H A Dbuild.info25 $CHACHAASM_riscv64=chacha_riscv.c chacha_enc.c chacha-riscv64-v-zbb.s chacha-riscv64-v-zbb-zvkb.s
56 GENERATE[chacha-riscv64-v-zbb.s]=asm/chacha-riscv64-v-zbb.pl
57 GENERATE[chacha-riscv64-v-zbb-zvkb.s]=asm/chacha-riscv64-v-zbb.pl zvkb
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsRISCV.td23 // Zbb extension.
25 def orc_b_32 : RISCVBuiltin<"unsigned int(unsigned int)", "zbb">;
26 def orc_b_64 : RISCVBuiltin<"uint64_t(uint64_t)", "zbb,64bit">;
27 def clz_32 : RISCVBuiltin<"unsigned int(unsigned int)", "zbb|xtheadbb">;
28 def clz_64 : RISCVBuiltin<"unsigned int(uint64_t)", "zbb|xtheadbb,64bit">;
29 def ctz_32 : RISCVBuiltin<"unsigned int(unsigned int)", "zbb">;
30 def ctz_64 : RISCVBuiltin<"unsigned int(uint64_t)", "zbb,64bit">;
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_riscvcap.394 zba/zbb/zbs would not be implied in the capability vector.
102 .IP ZBB 4
103 .IX Item "ZBB"
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_riscvcap.pod33 zba/zbb/zbs would not be implied in the capability vector.
45 =item ZBB
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVScheduleZb.td15 // Zbb extension
54 // Zbb extension
H A DRISCVSchedXiangShanNanHu.td82 // Zbb
105 // Zbb
280 // Zbb
H A DRISCVFeatures.td480 : RISCVExtension<"zbb", 1, 0,
481 "'Zbb' (Basic Bit-Manipulation)">,
485 "'Zbb' (Basic Bit-Manipulation)">;
509 "'B' (the collection of the Zba, Zbb, Zbs extensions)",
513 "'B' (the collection of the Zba, Zbb, Zbs extensions)">;
534 "'Zbb' (Basic Bit-Manipulation) or "
H A DRISCVInstrInfoSFB.td178 // Zbb/Zbkb instructions
H A DRISCVISelLowering.h140 // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
H A DRISCVInstrInfoZb.td12 // Zbb - 1.0
H A DRISCVISelDAGToDAG.cpp1183 // This can occur when Zbb is enabled, which makes sext_inreg i16/i8 legal. in Select()
1184 // This transform matches the code we get without Zbb. The shifts are more in Select()
H A DRISCVInstrInfo.td1678 // There are single-instruction versions of these in Zbb, so disable these
H A DRISCVISelLowering.cpp354 // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll in RISCVTargetLowering()
5690 // With Zbb, we can widen to i64 and smin/smax with INT32_MAX/MIN. in lowerSADDSAT_SSUBSAT()
5711 // With Zbb we can sign extend and let LegalizeDAG use minu/maxu. Using in lowerUADDSAT_USUBSAT()
12541 // With Zbb we can sign extend and let LegalizeDAG use minu/maxu. Using in ReplaceNodeResults()
12553 // Without Zbb, expand to UADDO/USUBO+select which will trigger our custom in ReplaceNodeResults()
17647 // With Zbb we can use sext.h/sext.b. in shouldTransformSignedTruncationCheck()
/freebsd/sys/net/
H A Dbpf_zerocopy.c529 struct zbuf *zba, *zbb; in bpf_zerocopy_ioctl_setzbuf() local
556 &zbb); in bpf_zerocopy_ioctl_setzbuf()
571 zbuf_free(zbb); in bpf_zerocopy_ioctl_setzbuf()
579 d->bd_fbuf = (caddr_t)zbb; in bpf_zerocopy_ioctl_setzbuf()
/freebsd/crypto/openssl/include/crypto/
H A Driscv_arch.def30 RISCV_DEFINE_CAP(ZBB, 0, 1, 4, (1 << 4))
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
94 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
127 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
160 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml201 - const: zbb
203 The standard Zbb bit-manipulation extension for basic bit-manipulation
/freebsd/share/misc/
H A Dcommitters-src.dot404 zbb [label="Zbigniew Bodek\nzbb@FreeBSD.org\n2013/09/02"]
507 cognet -> zbb
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-riscv64.pl138 # Compute GMULT (Xi*H mod f) using the Zbc (clmul) and Zbb (basic bit manip)
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DRISCV.cpp429 // EXTENSION like arch=+v,+zbb in parseTargetAttr()
/freebsd/crypto/openssl/crypto/chacha/asm/
H A Dchacha-riscv64-v-zbb.pl40 # - RISC-V Basic Bit-manipulation extension ('Zbb')
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp412 // Perform optimization with rori in the Zbb and th.srri in the XTheadBb in generateInstSeq()
/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm245 # rev8 without `rev8` instruction (only in Zbb or Zbkb)
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td91 // Zbb
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp2068 Features["zbb"] = ExtMask & (1 << 4); // RISCV_HWPROBE_EXT_ZBB in getHostCPUFeatures()

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