| /linux/drivers/spi/ |
| H A D | spi-xilinx.c | 116 static void xilinx_spi_tx(struct xilinx_spi *xspi) in xilinx_spi_tx() argument
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
127 data = *(u8 *)(xspi->tx_ptr); in xilinx_spi_tx()
130 data = *(u16 *)(xspi->tx_ptr); in xilinx_spi_tx()
133 data = *(u32 *)(xspi->tx_ptr); in xilinx_spi_tx()
137 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
138 xspi->tx_ptr += xspi->bytes_per_word; in xilinx_spi_tx()
141 static void xilinx_spi_rx(struct xilinx_spi *xspi) in xilinx_spi_rx() argument
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| H A D | spi-cadence.c | 134 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) in cdns_spi_read() argument
136 return readl_relaxed(xspi->regs + offset); in cdns_spi_read()
139 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) in cdns_spi_write() argument
141 writel_relaxed(val, xspi->regs + offset); in cdns_spi_write()
146 * @xspi: Pointer to the cdns_spi structure
156 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target) in cdns_spi_init_hw() argument
163 if (xspi->is_decoded_cs) in cdns_spi_init_hw()
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); in cdns_spi_init_hw()
167 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); in cdns_spi_init_hw()
170 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) in cdns_spi_init_hw()
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| H A D | spi-xlp.c | 125 static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi) in xlp_spi_sysctl_setup() argument
130 xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, in xlp_spi_sysctl_setup()
132 xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN); in xlp_spi_sysctl_setup()
137 struct xlp_spi_priv *xspi; in xlp_spi_setup() local
141 xspi = spi_controller_get_devdata(spi->controller); in xlp_spi_setup()
146 fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz); in xlp_spi_setup()
152 xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv); in xlp_spi_setup()
153 xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH); in xlp_spi_setup()
154 cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG); in xlp_spi_setup()
175 xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg); in xlp_spi_setup()
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| H A D | spi-cadence-xspi.c | 2 // Cadence XSPI flash controller driver
27 #define CDNS_XSPI_NAME "cadence-xspi"
31 * configure XSPI controller pin-strap settings
568 "Incorrect XSPI magic number: %x, expected: %x\n", in cdns_xspi_controller_init()
1273 .compatible = "cdns,xspi-nor",
1277 .compatible = "marvell,cn10-xspi-nor",
1294 MODULE_DESCRIPTION("Cadence XSPI Controller Driver");
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| /linux/drivers/memory/ |
| H A D | renesas-rpc-if.c | 22 #include "renesas-xspi-if-regs.h"
76 u8 addr_nbytes; /* Specified for xSPI */
77 u32 proto; /* Specified for xSPI */
180 struct rpcif_priv *xspi = context; in xspi_reg_read() local
182 *val = readl(xspi->base + reg); in xspi_reg_read()
188 struct rpcif_priv *xspi = context; in xspi_reg_write() local
190 writel(val, xspi->base + reg); in xspi_reg_write()
212 rpcif->xspi = rpc->info->type == XSPI_RZ_G3E; in rpcif_sw_init()
288 static int xspi_hw_init_impl(struct rpcif_priv *xspi, bool hyperflash) in xspi_hw_init_impl() argument
292 ret = reset_control_reset(xspi->rstc); in xspi_hw_init_impl()
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| H A D | renesas-xspi-if-regs.h | 3 * RZ xSPI Interface Registers Definitions
13 /* xSPI Wrapper Configuration Register */
16 /* xSPI Bridge Configuration Register */
23 /* xSPI Command Map Configuration Register 0 CS0 */
28 /* xSPI Command Map Configuration Register 1 CS0 */
34 /* xSPI Command Map Configuration Register 2 CS0 */
40 /* xSPI Link I/O Configuration Register CS0 */
47 /* xSPI Bridge Map Control Register 0 */
51 /* xSPI Bridge Map Control Register 1 */
55 /* xSPI Command Manual Control Register 0 */
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | renesas,rzg3e-xspi.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
7 title: Renesas Expanded Serial Peripheral Interface (xSPI)
13 Renesas xSPI allows a SPI flash connected to the SoC to be accessed via
16 The flash chip itself should be represented by a subnode of the XSPI node.
27 - const: renesas,r9a09g047-xspi # RZ/G3E
31 - renesas,r9a09g056-xspi # RZ/V2N
32 - renesas,r9a09g057-xspi # RZ/V2H(P)
33 - const: renesas,r9a09g047-xspi
37 - description: xSPI registers
82 renesas,xspi-cs-addr-sys:
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | cdns,xspi.yaml | 5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
8 title: Cadence XSPI Controller
14 The XSPI controller allows SPI protocol communication in
21 - cdns,xspi-nor
22 - marvell,cn10-xspi-nor
55 - marvell,cn10-xspi-nor
78 xspi: spi@a0010000 {
81 compatible = "cdns,xspi-nor";
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| /linux/include/dt-bindings/memory/ |
| H A D | tegra234-mc.h | 289 /* XSPI writes */
339 /* XSPI client */
341 /* XSPI writes */
343 /* XSPI client */
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| /linux/Documentation/devicetree/bindings/soc/renesas/ |
| H A D | renesas,r9a09g057-sys.yaml | 18 - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
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| /linux/include/memory/ |
| H A D | renesas-rpc-if.h | 71 bool xspi; member
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| /linux/drivers/mtd/spi-nor/ |
| H A D | sfdp.c | 24 #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 table. */
1106 * Since xSPI Page Program opcode is backward compatible with in spi_nor_parse_4bait()
1154 * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
1228 * Page Program is "Required Command" in the xSPI Profile 1.0. Update in spi_nor_parse_profile1()
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | rzg3e-smarc-som.dtsi | 369 &xspi {
|