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Searched +full:xs +full:- +full:phy (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
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/linux/drivers/phy/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek 10GE SerDes XFI T-PHY driver"
22 Say 'Y' here to add support for MediaTek XFI T-PHY driver.
23 The driver provides access to the Ethernet SerDes T-PHY supporting
28 tristate "MediaTek T-PHY Driver"
34 Say 'Y' here to add support for MediaTek T-PHY driver,
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H A Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
16 #include <linux/phy/phy.h>
19 #include "phy-mtk-io.h"
21 /* u2 phy banks */
26 /* u3 phy shared banks */
30 /* u3 phy banks */
85 struct phy *phy; member
87 struct clk *ref_clk; /* reference clock of anolog phy */
112 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
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/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
41 /* 0x0001 - 0x0003: reserved */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
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/linux/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
26 #define MDIO_MMD_POWER_UNIT 13 /* PHY Power Unit */
52 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
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/linux/drivers/net/bonding/
H A Dbond_main.c1 // SPDX-License-Identifier: GPL-1.0+
76 #include <linux/phy.h>
97 /*---------------------------- Module parameters ----------------------------*/
147 MODULE_PARM_DESC(mode, "Mode of operation; 0 for balance-rr, "
148 "1 for active-backup, 2 for balance-xor, "
149 "3 for broadcast, 4 for 802.3ad, 5 for balance-tlb, "
150 "6 for balance-alb");
172 MODULE_PARM_DESC(xmit_hash_policy, "balance-alb, balance-tlb, balance-xor, 802.3ad hashing method; "
187 MODULE_PARM_DESC(fail_over_mac, "For active-backup, do not set all slaves to "
198 MODULE_PARM_DESC(packets_per_slave, "Packets to send per slave in balance-rr "
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 static int debug = -1;
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
136 writel(val, hw->hw_addr + reg); in __ew32()
140 * e1000_regdump - register printout routine
150 switch (reginfo->ofs) { in e1000_regdump()
164 pr_info("%-15s %08x\n", in e1000_regdump()
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/linux/drivers/scsi/mpt3sas/
H A Dmpt3sas_base.c6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
57 #include <linux/dma-mapping.h>
75 static int max_queue_depth = -1;
79 static int max_sgl_entries = -1;
83 static int msix_disable = -1;
91 static int max_msix_vectors = -1;
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