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/linux/drivers/usb/host/
H A Dxhci-mem.c3 * xHCI host controller driver
19 #include "xhci.h"
20 #include "xhci-trace.h"
21 #include "xhci-debugfs.h"
30 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, in xhci_segment_alloc() argument
37 struct device *dev = xhci_to_hcd(xhci)->self.sysdev; in xhci_segment_alloc()
43 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); in xhci_segment_alloc()
53 dma_pool_free(xhci->segment_pool, seg->trbs, dma); in xhci_segment_alloc()
65 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) in xhci_segment_free() argument
68 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); in xhci_segment_free()
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H A Dxhci-ring.c3 * xHCI host controller driver
62 #include "xhci.h"
63 #include "xhci-trace.h"
65 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
188 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) in inc_deq() argument
211 xhci_warn(xhci, "Missing link TRB at end of segment\n"); in inc_deq()
223 xhci_warn(xhci, "Ring is an endless link TRB loop\n"); in inc_deq()
234 static void inc_enq_past_link(struct xhci_hcd *xhci, struct xhci_ring *ring, u32 chain) in inc_enq_past_link() argument
244 * xHCI hardware can't handle the chain bit being cleared on a link TRB. in inc_enq_past_link()
249 if (!xhci_link_chain_quirk(xhci, ring->type)) { in inc_enq_past_link()
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H A Dxhci-sideband.c4 * xHCI host controller sideband support
11 #include <linux/usb/xhci-sideband.h>
14 #include "xhci.h"
28 dev = xhci_to_hcd(sb->xhci)->self.sysdev; in xhci_ring_to_sgtable()
88 xhci_stop_endpoint_sync(sb->xhci, ep, 0, GFP_KERNEL); in __xhci_sideband_remove_endpoint()
103 xhci_remove_secondary_interrupter(xhci_to_hcd(sb->xhci), sb->ir); in __xhci_sideband_remove_interrupter()
114 * Notifies the xHCI sideband client driver of a xHCI transfer ring free
165 * smaller than for xhci it won't be able to access the endpoint ring in xhci_sideband_add_endpoint()
227 return xhci_stop_endpoint_sync(sb->xhci, ep, 0, GFP_KERNEL); in xhci_sideband_stop_endpoint()
265 * If a secondary xhci interupter is set up for this usb device then this
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H A Dxhci-debugfs.h3 * xhci-debugfs.h - xHCI debugfs interface
107 void xhci_debugfs_init(struct xhci_hcd *xhci);
108 void xhci_debugfs_exit(struct xhci_hcd *xhci);
111 void xhci_debugfs_create_slot(struct xhci_hcd *xhci, int slot_id);
112 void xhci_debugfs_remove_slot(struct xhci_hcd *xhci, int slot_id);
113 void xhci_debugfs_create_endpoint(struct xhci_hcd *xhci,
116 void xhci_debugfs_remove_endpoint(struct xhci_hcd *xhci,
119 void xhci_debugfs_create_stream_files(struct xhci_hcd *xhci,
123 static inline void xhci_debugfs_init(struct xhci_hcd *xhci) { } in xhci_debugfs_init() argument
124 static inline void xhci_debugfs_exit(struct xhci_hcd *xhci) { } in xhci_debugfs_exit() argument
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H A Dxhci-dbgcap.c3 * xhci-dbgcap.c - xHCI debug capability support
28 #include "xhci.h"
29 #include "xhci-trace.h"
30 #include "xhci-dbgcap.h"
452 /* xhci 7.6.9, all three contexts; info, ep-out and ep-in. Each 64 bytes*/ in dbc_alloc_ctx()
1131 struct xhci_hcd *xhci; in dbc_show() local
1133 xhci = hcd_to_xhci(dev_get_drvdata(dev)); in dbc_show()
1134 dbc = xhci->dbc; in dbc_show()
1149 struct xhci_hcd *xhci; in dbc_store() local
1152 xhci = hcd_to_xhci(dev_get_drvdata(dev)); in dbc_store()
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H A Dxhci-ext-caps.c3 * XHCI extended capability handling
11 #include "xhci.h"
28 static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset) in xhci_create_intel_xhci_sw_pdev() argument
30 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_create_intel_xhci_sw_pdev()
39 xhci_err(xhci, "couldn't allocate %s platform device\n", in xhci_create_intel_xhci_sw_pdev()
84 int xhci_ext_cap_init(struct xhci_hcd *xhci) in xhci_ext_cap_init() argument
86 void __iomem *base = &xhci->cap_regs->hc_capbase; in xhci_ext_cap_init()
97 if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { in xhci_ext_cap_init()
98 ret = xhci_create_intel_xhci_sw_pdev(xhci, in xhci_ext_cap_init()
H A Dxhci-dbg.c3 * xHCI host controller driver
11 #include "xhci.h"
13 char *xhci_get_slot_state(struct xhci_hcd *xhci, in xhci_get_slot_state() argument
16 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); in xhci_get_slot_state()
22 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), in xhci_dbg_trace() argument
31 xhci_dbg(xhci, "%pV\n", &vaf); in xhci_dbg_trace()
H A Dxhci-dbgcap.h3 * xhci-dbgcap.h - xHCI debug capability support
148 struct xhci_hcd *xhci; member
232 int xhci_create_dbc_dev(struct xhci_hcd *xhci);
233 void xhci_remove_dbc_dev(struct xhci_hcd *xhci);
238 int xhci_dbc_tty_probe(struct device *dev, void __iomem *res, struct xhci_hcd *xhci);
249 int xhci_dbc_suspend(struct xhci_hcd *xhci);
250 int xhci_dbc_resume(struct xhci_hcd *xhci);
253 static inline int xhci_create_dbc_dev(struct xhci_hcd *xhci) in xhci_create_dbc_dev() argument
258 static inline void xhci_remove_dbc_dev(struct xhci_hcd *xhci) in xhci_remove_dbc_dev() argument
268 static inline int xhci_dbc_suspend(struct xhci_hcd *xhci) in xhci_dbc_suspend() argument
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H A Dxhci-rzv2m.c3 * xHCI host controller driver for RZ/V2M
9 #include "xhci.h"
10 #include "xhci-plat.h"
11 #include "xhci-rzv2m.h"
H A Dxhci-mtk-sch.c13 #include "xhci.h"
14 #include "xhci-mtk.h"
130 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); in get_bw_info() local
134 virt_dev = xhci->devs[udev->slot_id]; in get_bw_info()
147 bw_index = virt_dev->rhub_port->hw_portnum + xhci->usb3_rhub.num_ports; in get_bw_info()
331 * xHCI spec section6.2.3.4 in setup_sch_info()
886 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); in xhci_mtk_sch_init() local
891 num_usb_bus = xhci->usb3_rhub.num_ports * 2 + xhci->usb2_rhub.num_ports; in xhci_mtk_sch_init()
914 struct xhci_hcd *xhci = hcd_to_xhci(hcd); in add_ep_quirk() local
920 virt_dev = xhci->devs[udev->slot_id]; in add_ep_quirk()
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/linux/Documentation/devicetree/bindings/usb/
H A Drenesas,usb-xhci.yaml4 $id: http://devicetree.org/schemas/usb/renesas,usb-xhci.yaml#
7 title: Renesas USB xHCI controllers
18 - renesas,xhci-r8a7742 # RZ/G1H
19 - renesas,xhci-r8a7743 # RZ/G1M
20 - renesas,xhci-r8a7744 # RZ/G1N
21 - renesas,xhci-r8a7790 # R-Car H2
22 - renesas,xhci-r8a7791 # R-Car M2-W
23 - renesas,xhci-r8a7793 # R-Car M2-N
24 - const: renesas,rcar-gen2-xhci # R-Car Gen2 and RZ/G1
27 - renesas,xhci-r8a774a1 # RZ/G2M
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H A Dgeneric-xhci.yaml4 $id: http://devicetree.org/schemas/usb/generic-xhci.yaml#
7 title: USB xHCI Controller
15 - description: Generic xHCI device
16 const: generic-xhci
20 - marvell,armada-375-xhci
21 - marvell,armada-380-xhci
25 - marvell,armada3700-xhci
26 - marvell,armada-8k-xhci
27 - const: generic-xhci
31 - brcm,bcm2711-xhci
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H A Dmediatek,mtk-xhci.yaml5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
8 title: MediaTek USB3 xHCI
14 - $ref: usb-xhci.yaml
18 case 1: only supports xHCI driver;
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
28 - mediatek,mt7622-xhci
29 - mediatek,mt7623-xhci
30 - mediatek,mt7629-xhci
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H A Drenesas,rzg3e-xhci.yaml4 $id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
17 - renesas,r9a09g056-xhci # RZ/V2N
18 - renesas,r9a09g057-xhci # RZ/V2H(P)
19 - const: renesas,r9a09g047-xhci
22 - const: renesas,r9a09g047-xhci # RZ/G3E
72 - $ref: usb-xhci.yaml
82 compatible = "renesas,r9a09g047-xhci";
H A Dnvidia,tegra234-xusb.yaml7 title: NVIDIA Tegra234 xHCI controller
14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
15 the Tegra XUSB pad controller. The xHCI controller controls up to eight
24 - description: xHCI host registers
37 - description: xHCI host interrupt
105 the USB pads used by the XHCI controller
138 - $ref: usb-xhci.yaml
H A Dnvidia,tegra186-xusb.yaml7 title: NVIDIA Tegra186 xHCI controller
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
22 - description: base and length of the xHCI host registers
32 - description: xHCI host interrupt
75 the USB pads used by the XHCI controller
126 - $ref: usb-xhci.yaml
H A Dnvidia,tegra194-xusb.yaml7 title: NVIDIA Tegra194 xHCI controller
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
22 - description: base and length of the xHCI host registers
32 - description: xHCI host interrupt
75 the USB pads used by the XHCI controller
127 - $ref: usb-xhci.yaml
H A Dhisilicon,histb-xhci.txt1 HiSilicon STB xHCI
3 The device node for HiSilicon STB xHCI host controller
6 - compatible: should be "hisilicon,hi3798cv200-xhci"
33 compatible = "hisilicon,hi3798cv200-xhci";
H A Dnvidia,tegra124-xusb.yaml7 title: NVIDIA Tegra124 xHCI controller
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
30 - description: base and length of the xHCI host registers
42 - description: xHCI host interrupt
88 the USB pads used by the XHCI controller
133 - $ref: usb-xhci.yaml
/linux/Documentation/devicetree/bindings/phy/
H A Drealtek,usb2phy.yaml15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
20 The USB architecture includes three XHCI controllers.
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
30 The USB architecture includes two XHCI controllers.
33 XHCI controller#0 -- usb2phy -- phy#0
34 XHCI controller#1 -- usb2phy -- phy#0
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H A Drealtek,usb3phy.yaml15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
20 The USB architecture includes three XHCI controllers.
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
30 The USB architecture includes three XHCI controllers.
31 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
32 XHCI controller#0 -- usb2phy -- phy#0
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H A Dbrcm,brcmstb-usb-phy.yaml9 description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
28 - description: XHCI EC register
29 - description: XHCI GBL register
88 brcm,has-xhci:
89 description: Indicates the PHY has an XHCI PHY.
109 - brcm,has-xhci
169 brcm,has-xhci;
195 brcm,has-xhci;
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-pci-drivers-xhci_hcd5 xHCI compatible USB host controllers (i.e. super-speed
12 The DbC debug device shares a root port with xHCI host.
15 to xHCI.
21 port will roll back to the xHCI.
32 presented in the USB device descriptor by this xhci debug
45 presented in the USB device descriptor by this xhci debug
57 presented in the USB device descriptor by this xhci debug
70 presented in the USB Interface descriptor by the xhci debug
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6usb.yaml15 XHCI host controller properly for enabling the offloaded audio stream.
18 the XHCI host controller.
36 Desired XHCI interrupter number to use. Depending on the audio DSP
37 on the platform, it will operate on a specific XHCI interrupter.
/linux/drivers/usb/early/
H A Dxhci-dbc.h3 * xhci-dbc.h - xHCI debug capability early driver
17 * xHCI Debug Capability Register interfaces:
53 * xHCI Debug Capability data structures:
107 * xHCI Debug Capability software state structures:
128 * Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer

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