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/linux/drivers/usb/host/
H A Dxhci.c3 * xHCI host controller driver
23 #include <linux/usb/xhci-sideband.h>
25 #include "xhci.h"
26 #include "xhci-trace.h"
27 #include "xhci-debugfs.h"
28 #include "xhci-dbgcap.h"
101 * Disable interrupts and begin the xHCI halting process.
103 void xhci_quiesce(struct xhci_hcd *xhci) in xhci_quiesce() argument
110 halted = readl(&xhci->op_regs->status) & STS_HALT; in xhci_quiesce()
114 cmd = readl(&xhci->op_regs->command); in xhci_quiesce()
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H A Dxhci-mem.c3 * xHCI host controller driver
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-debugfs.h"
29 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, in xhci_segment_alloc() argument
36 struct device *dev = xhci_to_hcd(xhci)->self.sysdev; in xhci_segment_alloc()
42 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); in xhci_segment_alloc()
52 dma_pool_free(xhci->segment_pool, seg->trbs, dma); in xhci_segment_alloc()
64 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) in xhci_segment_free() argument
67 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); in xhci_segment_free()
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H A Dxhci-pci.c3 * xHCI host controller driver PCI Bus Glue.
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-pci.h"
116 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) in xhci_msix_sync_irqs() argument
118 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_msix_sync_irqs()
129 static void xhci_cleanup_msix(struct xhci_hcd *xhci) in xhci_cleanup_msix() argument
131 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_cleanup_msix()
137 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); in xhci_cleanup_msix()
146 struct xhci_hcd *xhci = hcd_to_xhci(hcd); in xhci_try_enable_msi() local
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H A Dxhci-ring.c3 * xHCI host controller driver
60 #include "xhci.h"
61 #include "xhci-trace.h"
63 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
186 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) in inc_deq() argument
209 xhci_warn(xhci, "Missing link TRB at end of segment\n"); in inc_deq()
221 xhci_warn(xhci, "Ring is an endless link TRB loop\n"); in inc_deq()
232 static void inc_enq_past_link(struct xhci_hcd *xhci, struct xhci_ring *ring, u32 chain) in inc_enq_past_link() argument
242 * xHCI hardware can't handle the chain bit being cleared on a link TRB. in inc_enq_past_link()
247 if (!xhci_link_chain_quirk(xhci, ring->type)) { in inc_enq_past_link()
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H A Dxhci-hub.c3 * xHCI host controller driver
17 #include "xhci.h"
18 #include "xhci-trace.h"
36 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, in xhci_create_usb3x_bos_desc() argument
61 for (i = 0; i < xhci->num_port_caps; i++) { in xhci_create_usb3x_bos_desc()
62 u8 major = xhci->port_caps[i].maj_rev; in xhci_create_usb3x_bos_desc()
63 u8 minor = xhci->port_caps[i].min_rev; in xhci_create_usb3x_bos_desc()
68 port_cap = &xhci->port_caps[i]; in xhci_create_usb3x_bos_desc()
112 reg = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3x_bos_desc()
116 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { in xhci_create_usb3x_bos_desc()
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H A Dxhci-debugfs.c3 * xhci-debugfs.c - xHCI debugfs interface
13 #include "xhci.h"
14 #include "xhci-debugfs.h"
86 static struct xhci_regset *xhci_debugfs_alloc_regset(struct xhci_hcd *xhci) in xhci_debugfs_alloc_regset() argument
99 list_add_tail(&regset->list, &xhci->regset_list); in xhci_debugfs_alloc_regset()
114 static void xhci_debugfs_regset(struct xhci_hcd *xhci, u32 base, in xhci_debugfs_regset() argument
122 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_debugfs_regset()
124 rgs = xhci_debugfs_alloc_regset(xhci); in xhci_debugfs_regset()
141 static void xhci_debugfs_extcap_regset(struct xhci_hcd *xhci, int cap_id, in xhci_debugfs_extcap_regset() argument
148 void __iomem *base = &xhci->cap_regs->hc_capbase; in xhci_debugfs_extcap_regset()
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H A Dxhci-sideband.c4 * xHCI host controller sideband support
11 #include <linux/usb/xhci-sideband.h>
14 #include "xhci.h"
28 dev = xhci_to_hcd(sb->xhci)->self.sysdev; in xhci_ring_to_sgtable()
86 xhci_stop_endpoint_sync(sb->xhci, ep, 0, GFP_KERNEL); in __xhci_sideband_remove_endpoint()
103 xhci_remove_secondary_interrupter(xhci_to_hcd(sb->xhci), sb->ir); in __xhci_sideband_remove_interrupter()
118 * Notifies the xHCI sideband client driver of a xHCI transfer ring free
169 * smaller than for xhci it won't be able to access the endpoint ring in xhci_sideband_add_endpoint()
231 return xhci_stop_endpoint_sync(sb->xhci, ep, 0, GFP_KERNEL); in xhci_sideband_stop_endpoint()
269 * If a secondary xhci interupter is set up for this usb device then this
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H A Dxhci-mtk.c3 * MediaTek xHCI Host Controller Driver
24 #include "xhci.h"
25 #include "xhci-mtk.h"
61 /* xHCI CSR */
145 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) in xhci_mtk_set_frame_interval()
451 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) in xhci_mtk_quirks() argument
453 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_mtk_quirks()
456 xhci->quirks |= XHCI_MTK_HOST; in xhci_mtk_quirks()
461 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; in xhci_mtk_quirks()
463 xhci->quirks |= XHCI_LPM_SUPPORT; in xhci_mtk_quirks()
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H A Dxhci.h4 * xHCI host controller driver
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
32 /* xHCI PCI Configuration Registers */
38 * Max Number of Ports. xHCI specification section 5.3.3
43 * Max number of Interrupter Register Sets. xHCI specification section 5.3.3
49 * xHCI register interface.
50 * This corresponds to the eXtensible Host Controller Interface (xHCI)
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H A Dxhci-debugfs.h3 * xhci-debugfs.h - xHCI debugfs interface
107 void xhci_debugfs_init(struct xhci_hcd *xhci);
108 void xhci_debugfs_exit(struct xhci_hcd *xhci);
111 void xhci_debugfs_create_slot(struct xhci_hcd *xhci, int slot_id);
112 void xhci_debugfs_remove_slot(struct xhci_hcd *xhci, int slot_id);
113 void xhci_debugfs_create_endpoint(struct xhci_hcd *xhci,
116 void xhci_debugfs_remove_endpoint(struct xhci_hcd *xhci,
119 void xhci_debugfs_create_stream_files(struct xhci_hcd *xhci,
123 static inline void xhci_debugfs_init(struct xhci_hcd *xhci) { } in xhci_debugfs_init() argument
124 static inline void xhci_debugfs_exit(struct xhci_hcd *xhci) { } in xhci_debugfs_exit() argument
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H A Dxhci-dbgcap.c3 * xhci-dbgcap.c - xHCI debug capability support
28 #include "xhci.h"
29 #include "xhci-trace.h"
30 #include "xhci-dbgcap.h"
453 /* xhci 7.6.9, all three contexts; info, ep-out and ep-in. Each 64 bytes*/ in dbc_alloc_ctx()
1057 struct xhci_hcd *xhci; in dbc_show() local
1059 xhci = hcd_to_xhci(dev_get_drvdata(dev)); in dbc_show()
1060 dbc = xhci->dbc; in dbc_show()
1072 struct xhci_hcd *xhci; in dbc_store() local
1075 xhci = hcd_to_xhci(dev_get_drvdata(dev)); in dbc_store()
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H A Dxhci-ext-caps.c3 * XHCI extended capability handling
11 #include "xhci.h"
28 static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset) in xhci_create_intel_xhci_sw_pdev() argument
30 struct usb_hcd *hcd = xhci_to_hcd(xhci); in xhci_create_intel_xhci_sw_pdev()
39 xhci_err(xhci, "couldn't allocate %s platform device\n", in xhci_create_intel_xhci_sw_pdev()
84 int xhci_ext_cap_init(struct xhci_hcd *xhci) in xhci_ext_cap_init() argument
86 void __iomem *base = &xhci->cap_regs->hc_capbase; in xhci_ext_cap_init()
97 if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { in xhci_ext_cap_init()
98 ret = xhci_create_intel_xhci_sw_pdev(xhci, in xhci_ext_cap_init()
H A Dxhci-dbg.c3 * xHCI host controller driver
11 #include "xhci.h"
13 char *xhci_get_slot_state(struct xhci_hcd *xhci, in xhci_get_slot_state() argument
16 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); in xhci_get_slot_state()
22 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), in xhci_dbg_trace() argument
31 xhci_dbg(xhci, "%pV\n", &vaf); in xhci_dbg_trace()
H A Dxhci-mtk-sch.c13 #include "xhci.h"
14 #include "xhci-mtk.h"
130 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); in get_bw_info() local
134 virt_dev = xhci->devs[udev->slot_id]; in get_bw_info()
147 bw_index = virt_dev->rhub_port->hw_portnum + xhci->usb3_rhub.num_ports; in get_bw_info()
331 * xHCI spec section6.2.3.4 in setup_sch_info()
886 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); in xhci_mtk_sch_init() local
891 num_usb_bus = xhci->usb3_rhub.num_ports * 2 + xhci->usb2_rhub.num_ports; in xhci_mtk_sch_init()
914 struct xhci_hcd *xhci = hcd_to_xhci(hcd); in add_ep_quirk() local
920 virt_dev = xhci->devs[udev->slot_id]; in add_ep_quirk()
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H A Dxhci-rzv2m.c3 * xHCI host controller driver for RZ/V2M
9 #include "xhci.h"
10 #include "xhci-plat.h"
11 #include "xhci-rzv2m.h"
/linux/Documentation/devicetree/bindings/usb/
H A Drenesas,usb-xhci.yaml4 $id: http://devicetree.org/schemas/usb/renesas,usb-xhci.yaml#
7 title: Renesas USB xHCI controllers
18 - renesas,xhci-r8a7742 # RZ/G1H
19 - renesas,xhci-r8a7743 # RZ/G1M
20 - renesas,xhci-r8a7744 # RZ/G1N
21 - renesas,xhci-r8a7790 # R-Car H2
22 - renesas,xhci-r8a7791 # R-Car M2-W
23 - renesas,xhci-r8a7793 # R-Car M2-N
24 - const: renesas,rcar-gen2-xhci # R-Car Gen2 and RZ/G1
27 - renesas,xhci-r8a774a1 # RZ/G2M
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H A Dgeneric-xhci.yaml4 $id: http://devicetree.org/schemas/usb/generic-xhci.yaml#
7 title: USB xHCI Controller
15 - description: Generic xHCI device
16 const: generic-xhci
20 - marvell,armada-375-xhci
21 - marvell,armada-380-xhci
25 - marvell,armada3700-xhci
26 - marvell,armada-8k-xhci
27 - const: generic-xhci
31 - brcm,bcm2711-xhci
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H A Dmediatek,mtk-xhci.yaml5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
8 title: MediaTek USB3 xHCI
14 - $ref: usb-xhci.yaml
18 case 1: only supports xHCI driver;
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
28 - mediatek,mt7622-xhci
29 - mediatek,mt7623-xhci
30 - mediatek,mt7629-xhci
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H A Drenesas,rzg3e-xhci.yaml4 $id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
17 - renesas,r9a09g056-xhci # RZ/V2N
18 - renesas,r9a09g057-xhci # RZ/V2H(P)
19 - const: renesas,r9a09g047-xhci
22 - const: renesas,r9a09g047-xhci # RZ/G3E
72 - $ref: usb-xhci.yaml
82 compatible = "renesas,r9a09g047-xhci";
H A Dmediatek,mtu3.yaml18 based on xHCI.
186 layer between xHCI and SPM, the field should always be 3 cells long.
220 $ref: /schemas/usb/mediatek,mtk-xhci.yaml#
222 The xhci should be added as subnode to mtu3 as shown in the following
269 xhci: usb@11270000 {
270 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
302 compatible = "mediatek,mt2712-xhci", "mediatek,mtk-xhci";
339 compatible = "mediatek,mt8183-xhci", "mediatek,mtk-xhci";
H A Dnvidia,tegra234-xusb.yaml7 title: NVIDIA Tegra234 xHCI controller
14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
15 the Tegra XUSB pad controller. The xHCI controller controls up to eight
24 - description: xHCI host registers
37 - description: xHCI host interrupt
105 the USB pads used by the XHCI controller
138 - $ref: usb-xhci.yaml
/linux/drivers/usb/dwc3/
H A Dhost.c16 #include "../host/xhci-port.h"
17 #include "../host/xhci-ext-caps.h"
18 #include "../host/xhci-caps.h"
19 #include "../host/xhci-plat.h"
38 /* xhci regs are not mapped yet, do it temporarily here */ in dwc3_power_off_all_roothub_ports()
62 dev_err(dwc->dev, "xhci base reg invalid\n"); in dwc3_power_off_all_roothub_ports()
133 struct platform_device *xhci; in dwc3_host_init() local
139 * mode to avoid VBUS glitch happen when xhci get reset later. in dwc3_host_init()
147 xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO); in dwc3_host_init()
148 if (!xhci) { in dwc3_host_init()
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/linux/Documentation/devicetree/bindings/phy/
H A Drealtek,usb2phy.yaml15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
20 The USB architecture includes three XHCI controllers.
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
30 The USB architecture includes two XHCI controllers.
33 XHCI controller#0 -- usb2phy -- phy#0
34 XHCI controller#1 -- usb2phy -- phy#0
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H A Drealtek,usb3phy.yaml15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
20 The USB architecture includes three XHCI controllers.
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
30 The USB architecture includes three XHCI controllers.
31 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
32 XHCI controller#0 -- usb2phy -- phy#0
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H A Dbrcm,brcmstb-usb-phy.yaml9 description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
28 - description: XHCI EC register
29 - description: XHCI GBL register
88 brcm,has-xhci:
89 description: Indicates the PHY has an XHCI PHY.
109 - brcm,has-xhci
169 brcm,has-xhci;
195 brcm,has-xhci;

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