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/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_blocks.h21 #define PCI_RD_REGULATOR_SECTION 0x1000
30 #define MME1_RD_REGULATOR_SECTION 0x1000
39 #define MME2_RD_REGULATOR_SECTION 0x1000
48 #define MME3_RD_REGULATOR_SECTION 0x1000
57 #define MME_QM_SECTION 0x1000
60 #define MME_CMDQ_SECTION 0x1000
63 #define ACC_MS_ECC_MEM_0_SECTION 0x1000
66 #define ACC_MS_ECC_MEM_1_SECTION 0x1000
69 #define ACC_MS_ECC_MEM_2_SECTION 0x1000
72 #define ACC_MS_ECC_MEM_3_SECTION 0x1000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h23 #define MME0_SBAB_SECTION 0x1000
188 #define MME1_SBAB_SECTION 0x1000
353 #define MME2_SBAB_SECTION 0x1000
518 #define MME3_SBAB_SECTION 0x1000
680 #define SRAM_Y0_X0_BANK_SECTION 0x1000
686 #define SRAM_Y0_X1_BANK_SECTION 0x1000
692 #define SRAM_Y0_X2_BANK_SECTION 0x1000
698 #define SRAM_Y0_X3_BANK_SECTION 0x1000
704 #define SRAM_Y0_X4_BANK_SECTION 0x1000
710 #define SRAM_Y0_X5_BANK_SECTION 0x1000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
26 #define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000
29 #define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000
30 #define DCORE0_TPC0_EML_CTI_SECTION 0x1000
32 #define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi193 reg = <0x0 0x1000>;
197 reg = <0x1000 0x1000 0x1002000 0x10000>;
201 reg = <0x2000 0x1000>;
205 reg = <0x8000 0x1000 0x1A000 0x1000>;
209 reg = <0x9000 0x1000>;
213 reg = <0x11000 0x1000>;
218 reg = <0x12000 0x1000>;
223 reg = <0x13000 0x1000>;
228 reg = <0x14000 0x1000>;
232 reg = <0x18000 0x1000>;
[all …]
H A Db4si-post.dtsi96 reg = <0x0 0x1000>;
100 reg = <0x1000 0x1000 0x1002000 0x10000>;
104 reg = <0x2000 0x1000>;
108 reg = <0x8000 0x1000 0x1A000 0x1000>;
112 reg = <0x9000 0x1000>;
116 reg = <0x11000 0x1000>;
121 reg = <0x12000 0x1000>;
125 reg = <0x18000 0x1000>;
129 reg = <0x22000 0x1000>;
133 reg = <0x30000 0x1000 0x1022000 0x10000>;
[all …]
H A Dt2081si-post.dtsi177 reg = <0x0 0x1000>;
181 reg = <0x1000 0x1000 0x1002000 0x10000>;
185 reg = <0x2000 0x1000>;
189 reg = <0x8000 0x1000 0x1A000 0x1000>;
193 reg = <0x11000 0x1000>;
198 reg = <0x12000 0x1000>;
202 reg = <0x18000 0x1000>;
206 reg = <0x22000 0x1000>;
210 reg = <0x30000 0x1000 0x1022000 0x10000>;
214 reg = <0x31000 0x1000 0x1042000 0x10000>;
[all …]
H A Db4860si-post.dtsi79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
123 reg = <0x40000 0x4000>, <0x1010000 0x1000>;
128 reg = <0x44000 0x4000>, <0x1011000 0x1000>;
133 reg = <0x48000 0x4000>, <0x1012000 0x1000>;
138 reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
[all …]
H A Dt1040si-post.dtsi173 reg = <0x0 0x1000>;
177 reg = <0x1000 0x1000 0x1002000 0x10000>;
181 reg = <0x2000 0x1000>;
185 reg = <0x8000 0x1000 0x1A000 0x1000>;
189 reg = <0x9000 0x1000>;
193 reg = <0x11000 0x1000>;
198 reg = <0x12000 0x1000>;
202 reg = <0x18000 0x1000>;
206 reg = <0x22000 0x1000>;
210 reg = <0x30000 0x1000 0x1022000 0x10000>;
[all …]
H A Dt1023si-post.dtsi147 reg = <0x0 0x1000>;
151 reg = <0x1000 0x1000 0x1002000 0x10000>;
155 reg = <0x2000 0x1000>;
159 reg = <0x8000 0x1000 0x1A000 0x1000>;
163 reg = <0x11000 0x1000>;
168 reg = <0x12000 0x1000>;
172 reg = <0x18000 0x1000>;
176 reg = <0x22000 0x1000>;
180 reg = <0x30000 0x1000 0x1022000 0x10000>;
184 reg = <0x31000 0x1000 0x1042000 0x10000>;
[all …]
H A Dp4080si-post.dtsi178 reg = <0x0 0x1000>;
182 reg = <0x1000 0x1000 0x1000000 0x8000>;
186 reg = <0x2000 0x1000>;
190 reg = <0x8000 0x1000 0xB0000 0x1000>;
194 reg = <0x9000 0x1000>;
198 reg = <0x11000 0x1000>;
203 reg = <0x12000 0x1000>;
208 reg = <0x13000 0x1000>;
212 reg = <0x18000 0x1000>;
216 reg = <0x22000 0x1000>;
[all …]
H A Dp5040si-post.dtsi151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
163 reg = <0x8000 0x1000 0xB0000 0x1000>;
167 reg = <0x9000 0x1000>;
171 reg = <0x11000 0x1000>;
176 reg = <0x12000 0x1000>;
181 reg = <0x13000 0x1000>;
185 reg = <0x18000 0x1000>;
189 reg = <0x22000 0x1000>;
[all …]
/linux/sound/soc/qcom/
H A Dlpass-apq8016.c227 .i2sctrl_reg_base = 0x1000,
228 .i2sctrl_reg_stride = 0x1000,
231 .irq_reg_stride = 0x1000,
234 .rdma_reg_stride = 0x1000,
238 .wrdma_reg_stride = 0x1000,
241 .loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
242 .spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
243 .spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
244 .spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
245 .micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
9 compatible = "ingenic,x1000", "ingenic,x1000e";
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
54 cgu: x1000-cgu@10000000 {
55 compatible = "ingenic,x1000-cgu", "simple-mfd";
67 compatible = "ingenic,x1000-phy";
78 compatible = "ingenic,x1000-rng";
91 compatible = "ingenic,x1000-ost";
104 compatible = "ingenic,x1000-tcu", "simple-mfd";
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
H A Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhisi-x5hd2.dtsi23 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
41 reg = <0x00002000 0x1000>;
55 reg = <0x00a29000 0x1000>;
64 reg = <0x00a2a000 0x1000>;
73 reg = <0x00a2b000 0x1000>;
82 reg = <0x00a81000 0x1000>;
91 reg = <0x00b00000 0x1000>;
100 reg = <0x00006000 0x1000>;
109 reg = <0x00b02000 0x1000>;
118 reg = <0x00b03000 0x1000>;
[all …]
H A Dhi3620.dtsi88 reg = <0x1000 0x1000>, <0x100 0x100>;
95 ranges = <0 0x802000 0x1000>;
96 reg = <0x802000 0x1000>;
111 reg = <0x800000 0x1000>;
123 reg = <0x801000 0x1000>;
135 reg = <0xa01000 0x1000>;
147 reg = <0xa02000 0x1000>;
159 reg = <0xa03000 0x1000>;
177 reg = <0xb00000 0x1000>;
186 reg = <0xb01000 0x1000>;
[all …]
/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi84 reg = <0xa9000000 0x1000>;
89 reg = <0xb0000000 0x1000>;
97 reg = <0xb4000000 0x1000>;
104 reg = <0xc0000000 0x1000>;
118 reg = <0xc4000000 0x1000>;
123 reg = <0xc8010000 0x1000>;
127 reg = <0xcc000000 0x1000>;
139 reg = <0x90000000 0x1000>;
146 reg = <0x90010000 0x1000>;
151 reg = <0x90020000 0x1000>;
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8196-pinctrl.yaml197 reg = <0x1002d000 0x1000>,
198 <0x12000000 0x1000>,
199 <0x12020000 0x1000>,
200 <0x12040000 0x1000>,
201 <0x12060000 0x1000>,
202 <0x12820000 0x1000>,
203 <0x12840000 0x1000>,
204 <0x12860000 0x1000>,
205 <0x13000000 0x1000>,
206 <0x13020000 0x1000>,
[all …]
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c49 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
51 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
53 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
55 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
57 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
59 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
61 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
63 0x1000, BIT(2), 0, 0);
65 0x1000, BIT(18), 0, 0);
67 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
[all …]
H A Dsc9863a-clk.c27 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
29 0x1000, BIT(0), 0, 0, 240);
31 0x1000, BIT(0), 0, 0, 240);
33 0x1000, BIT(0), 0, 0, 240);
35 0x1000, BIT(0), 0, 0, 240);
37 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
39 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
41 0x1e8, 0x1000, BIT(0), 0, 0, 240);
233 0x4, 0x1000, BIT(8), 0, 0);
1054 static SPRD_SC_GATE_CLK_HW(otg_eb, "otg-eb", &ap_axi.common.hw, 0x0, 0x1000,
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear600.dtsi35 reg = <0xf1100000 0x1000>;
42 reg = <0xf1000000 0x1000>;
48 reg = <0xfc200000 0x1000>;
56 reg = <0xfc400000 0x1000>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
88 reg = <0xfc000000 0x1000>;
96 reg = <0xe1800000 0x1000>;
104 reg = <0xe2000000 0x1000>;
112 reg = <0xe1900000 0x1000>;
120 reg = <0xe2100000 0x1000>;
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dinterlaken-lac.txt32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
169 reg = <0x0 0x1000>;
175 reg = <0x1000 0x1000>;
181 reg = <0x2000 0x1000>;
187 reg = <0x3000 0x1000>;
193 reg = <0x4000 0x1000>;
199 reg = <0x5000 0x1000>;
205 reg = <0x6000 0x1000>;
[all …]
/linux/drivers/rapidio/devices/
H A Dtsi721.h146 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
150 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
153 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
157 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
160 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
163 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
165 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
166 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
171 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
172 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi15 reg = <0 0xf6401000 0 0x1000>;
40 reg = <0 0xf6402000 0 0x1000>;
101 reg = <0 0xf6404000 0 0x1000>;
117 reg = <0 0xf6405000 0 0x1000>;
133 reg = <0 0xf6501000 0 0x1000>;
218 reg = <0 0xf659c000 0 0x1000>;
237 reg = <0 0xf659d000 0 0x1000>;
256 reg = <0 0xf659e000 0 0x1000>;
275 reg = <0 0xf659f000 0 0x1000>;
294 reg = <0 0xf65dc000 0 0x1000>;
[all …]

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