1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef GOYA_BLOCKS_H_ 14*e65e175bSOded Gabbay #define GOYA_BLOCKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay #define mmPCI_NRTR_BASE 0x7FFC000000ull 17*e65e175bSOded Gabbay #define PCI_NRTR_MAX_OFFSET 0x608 18*e65e175bSOded Gabbay #define PCI_NRTR_SECTION 0x4000 19*e65e175bSOded Gabbay #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull 20*e65e175bSOded Gabbay #define PCI_RD_REGULATOR_MAX_OFFSET 0x74 21*e65e175bSOded Gabbay #define PCI_RD_REGULATOR_SECTION 0x1000 22*e65e175bSOded Gabbay #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull 23*e65e175bSOded Gabbay #define PCI_WR_REGULATOR_MAX_OFFSET 0x74 24*e65e175bSOded Gabbay #define PCI_WR_REGULATOR_SECTION 0x3B000 25*e65e175bSOded Gabbay #define mmMME1_RTR_BASE 0x7FFC040000ull 26*e65e175bSOded Gabbay #define MME1_RTR_MAX_OFFSET 0x608 27*e65e175bSOded Gabbay #define MME1_RTR_SECTION 0x4000 28*e65e175bSOded Gabbay #define mmMME1_RD_REGULATOR_BASE 0x7FFC044000ull 29*e65e175bSOded Gabbay #define MME1_RD_REGULATOR_MAX_OFFSET 0x74 30*e65e175bSOded Gabbay #define MME1_RD_REGULATOR_SECTION 0x1000 31*e65e175bSOded Gabbay #define mmMME1_WR_REGULATOR_BASE 0x7FFC045000ull 32*e65e175bSOded Gabbay #define MME1_WR_REGULATOR_MAX_OFFSET 0x74 33*e65e175bSOded Gabbay #define MME1_WR_REGULATOR_SECTION 0x3B000 34*e65e175bSOded Gabbay #define mmMME2_RTR_BASE 0x7FFC080000ull 35*e65e175bSOded Gabbay #define MME2_RTR_MAX_OFFSET 0x608 36*e65e175bSOded Gabbay #define MME2_RTR_SECTION 0x4000 37*e65e175bSOded Gabbay #define mmMME2_RD_REGULATOR_BASE 0x7FFC084000ull 38*e65e175bSOded Gabbay #define MME2_RD_REGULATOR_MAX_OFFSET 0x74 39*e65e175bSOded Gabbay #define MME2_RD_REGULATOR_SECTION 0x1000 40*e65e175bSOded Gabbay #define mmMME2_WR_REGULATOR_BASE 0x7FFC085000ull 41*e65e175bSOded Gabbay #define MME2_WR_REGULATOR_MAX_OFFSET 0x74 42*e65e175bSOded Gabbay #define MME2_WR_REGULATOR_SECTION 0x3B000 43*e65e175bSOded Gabbay #define mmMME3_RTR_BASE 0x7FFC0C0000ull 44*e65e175bSOded Gabbay #define MME3_RTR_MAX_OFFSET 0x608 45*e65e175bSOded Gabbay #define MME3_RTR_SECTION 0x4000 46*e65e175bSOded Gabbay #define mmMME3_RD_REGULATOR_BASE 0x7FFC0C4000ull 47*e65e175bSOded Gabbay #define MME3_RD_REGULATOR_MAX_OFFSET 0x74 48*e65e175bSOded Gabbay #define MME3_RD_REGULATOR_SECTION 0x1000 49*e65e175bSOded Gabbay #define mmMME3_WR_REGULATOR_BASE 0x7FFC0C5000ull 50*e65e175bSOded Gabbay #define MME3_WR_REGULATOR_MAX_OFFSET 0x74 51*e65e175bSOded Gabbay #define MME3_WR_REGULATOR_SECTION 0xB000 52*e65e175bSOded Gabbay #define mmMME_BASE 0x7FFC0D0000ull 53*e65e175bSOded Gabbay #define MME_MAX_OFFSET 0xBB0 54*e65e175bSOded Gabbay #define MME_SECTION 0x8000 55*e65e175bSOded Gabbay #define mmMME_QM_BASE 0x7FFC0D8000ull 56*e65e175bSOded Gabbay #define MME_QM_MAX_OFFSET 0x310 57*e65e175bSOded Gabbay #define MME_QM_SECTION 0x1000 58*e65e175bSOded Gabbay #define mmMME_CMDQ_BASE 0x7FFC0D9000ull 59*e65e175bSOded Gabbay #define MME_CMDQ_MAX_OFFSET 0x310 60*e65e175bSOded Gabbay #define MME_CMDQ_SECTION 0x1000 61*e65e175bSOded Gabbay #define mmACC_MS_ECC_MEM_0_BASE 0x7FFC0DA000ull 62*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_0_MAX_OFFSET 0x0 63*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_0_SECTION 0x1000 64*e65e175bSOded Gabbay #define mmACC_MS_ECC_MEM_1_BASE 0x7FFC0DB000ull 65*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_1_MAX_OFFSET 0x0 66*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_1_SECTION 0x1000 67*e65e175bSOded Gabbay #define mmACC_MS_ECC_MEM_2_BASE 0x7FFC0DC000ull 68*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_2_MAX_OFFSET 0x0 69*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_2_SECTION 0x1000 70*e65e175bSOded Gabbay #define mmACC_MS_ECC_MEM_3_BASE 0x7FFC0DD000ull 71*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_3_MAX_OFFSET 0x0 72*e65e175bSOded Gabbay #define ACC_MS_ECC_MEM_3_SECTION 0x1000 73*e65e175bSOded Gabbay #define mmSBA_ECC_MEM_BASE 0x7FFC0DE000ull 74*e65e175bSOded Gabbay #define SBA_ECC_MEM_MAX_OFFSET 0x0 75*e65e175bSOded Gabbay #define SBA_ECC_MEM_SECTION 0x1000 76*e65e175bSOded Gabbay #define mmSBB_ECC_MEM_BASE 0x7FFC0DF000ull 77*e65e175bSOded Gabbay #define SBB_ECC_MEM_MAX_OFFSET 0x0 78*e65e175bSOded Gabbay #define SBB_ECC_MEM_SECTION 0x21000 79*e65e175bSOded Gabbay #define mmMME4_RTR_BASE 0x7FFC100000ull 80*e65e175bSOded Gabbay #define MME4_RTR_MAX_OFFSET 0x608 81*e65e175bSOded Gabbay #define MME4_RTR_SECTION 0x4000 82*e65e175bSOded Gabbay #define mmMME4_RD_REGULATOR_BASE 0x7FFC104000ull 83*e65e175bSOded Gabbay #define MME4_RD_REGULATOR_MAX_OFFSET 0x74 84*e65e175bSOded Gabbay #define MME4_RD_REGULATOR_SECTION 0x1000 85*e65e175bSOded Gabbay #define mmMME4_WR_REGULATOR_BASE 0x7FFC105000ull 86*e65e175bSOded Gabbay #define MME4_WR_REGULATOR_MAX_OFFSET 0x74 87*e65e175bSOded Gabbay #define MME4_WR_REGULATOR_SECTION 0xB000 88*e65e175bSOded Gabbay #define mmSYNC_MNGR_BASE 0x7FFC110000ull 89*e65e175bSOded Gabbay #define SYNC_MNGR_MAX_OFFSET 0x4400 90*e65e175bSOded Gabbay #define SYNC_MNGR_SECTION 0x30000 91*e65e175bSOded Gabbay #define mmMME5_RTR_BASE 0x7FFC140000ull 92*e65e175bSOded Gabbay #define MME5_RTR_MAX_OFFSET 0x608 93*e65e175bSOded Gabbay #define MME5_RTR_SECTION 0x4000 94*e65e175bSOded Gabbay #define mmMME5_RD_REGULATOR_BASE 0x7FFC144000ull 95*e65e175bSOded Gabbay #define MME5_RD_REGULATOR_MAX_OFFSET 0x74 96*e65e175bSOded Gabbay #define MME5_RD_REGULATOR_SECTION 0x1000 97*e65e175bSOded Gabbay #define mmMME5_WR_REGULATOR_BASE 0x7FFC145000ull 98*e65e175bSOded Gabbay #define MME5_WR_REGULATOR_MAX_OFFSET 0x74 99*e65e175bSOded Gabbay #define MME5_WR_REGULATOR_SECTION 0x3B000 100*e65e175bSOded Gabbay #define mmMME6_RTR_BASE 0x7FFC180000ull 101*e65e175bSOded Gabbay #define MME6_RTR_MAX_OFFSET 0x608 102*e65e175bSOded Gabbay #define MME6_RTR_SECTION 0x4000 103*e65e175bSOded Gabbay #define mmMME6_RD_REGULATOR_BASE 0x7FFC184000ull 104*e65e175bSOded Gabbay #define MME6_RD_REGULATOR_MAX_OFFSET 0x74 105*e65e175bSOded Gabbay #define MME6_RD_REGULATOR_SECTION 0x1000 106*e65e175bSOded Gabbay #define mmMME6_WR_REGULATOR_BASE 0x7FFC185000ull 107*e65e175bSOded Gabbay #define MME6_WR_REGULATOR_MAX_OFFSET 0x74 108*e65e175bSOded Gabbay #define MME6_WR_REGULATOR_SECTION 0x3B000 109*e65e175bSOded Gabbay #define mmDMA_NRTR_BASE 0x7FFC1C0000ull 110*e65e175bSOded Gabbay #define DMA_NRTR_MAX_OFFSET 0x608 111*e65e175bSOded Gabbay #define DMA_NRTR_SECTION 0x4000 112*e65e175bSOded Gabbay #define mmDMA_RD_REGULATOR_BASE 0x7FFC1C4000ull 113*e65e175bSOded Gabbay #define DMA_RD_REGULATOR_MAX_OFFSET 0x74 114*e65e175bSOded Gabbay #define DMA_RD_REGULATOR_SECTION 0x1000 115*e65e175bSOded Gabbay #define mmDMA_WR_REGULATOR_BASE 0x7FFC1C5000ull 116*e65e175bSOded Gabbay #define DMA_WR_REGULATOR_MAX_OFFSET 0x74 117*e65e175bSOded Gabbay #define DMA_WR_REGULATOR_SECTION 0x3B000 118*e65e175bSOded Gabbay #define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull 119*e65e175bSOded Gabbay #define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4 120*e65e175bSOded Gabbay #define SRAM_Y0_X0_BANK_SECTION 0x1000 121*e65e175bSOded Gabbay #define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull 122*e65e175bSOded Gabbay #define SRAM_Y0_X0_RTR_MAX_OFFSET 0x334 123*e65e175bSOded Gabbay #define SRAM_Y0_X0_RTR_SECTION 0x3000 124*e65e175bSOded Gabbay #define mmSRAM_Y0_X1_BANK_BASE 0x7FFC204000ull 125*e65e175bSOded Gabbay #define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4 126*e65e175bSOded Gabbay #define SRAM_Y0_X1_BANK_SECTION 0x1000 127*e65e175bSOded Gabbay #define mmSRAM_Y0_X1_RTR_BASE 0x7FFC205000ull 128*e65e175bSOded Gabbay #define SRAM_Y0_X1_RTR_MAX_OFFSET 0x334 129*e65e175bSOded Gabbay #define SRAM_Y0_X1_RTR_SECTION 0x3000 130*e65e175bSOded Gabbay #define mmSRAM_Y0_X2_BANK_BASE 0x7FFC208000ull 131*e65e175bSOded Gabbay #define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4 132*e65e175bSOded Gabbay #define SRAM_Y0_X2_BANK_SECTION 0x1000 133*e65e175bSOded Gabbay #define mmSRAM_Y0_X2_RTR_BASE 0x7FFC209000ull 134*e65e175bSOded Gabbay #define SRAM_Y0_X2_RTR_MAX_OFFSET 0x334 135*e65e175bSOded Gabbay #define SRAM_Y0_X2_RTR_SECTION 0x3000 136*e65e175bSOded Gabbay #define mmSRAM_Y0_X3_BANK_BASE 0x7FFC20C000ull 137*e65e175bSOded Gabbay #define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4 138*e65e175bSOded Gabbay #define SRAM_Y0_X3_BANK_SECTION 0x1000 139*e65e175bSOded Gabbay #define mmSRAM_Y0_X3_RTR_BASE 0x7FFC20D000ull 140*e65e175bSOded Gabbay #define SRAM_Y0_X3_RTR_MAX_OFFSET 0x334 141*e65e175bSOded Gabbay #define SRAM_Y0_X3_RTR_SECTION 0x3000 142*e65e175bSOded Gabbay #define mmSRAM_Y0_X4_BANK_BASE 0x7FFC210000ull 143*e65e175bSOded Gabbay #define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4 144*e65e175bSOded Gabbay #define SRAM_Y0_X4_BANK_SECTION 0x1000 145*e65e175bSOded Gabbay #define mmSRAM_Y0_X4_RTR_BASE 0x7FFC211000ull 146*e65e175bSOded Gabbay #define SRAM_Y0_X4_RTR_MAX_OFFSET 0x334 147*e65e175bSOded Gabbay #define SRAM_Y0_X4_RTR_SECTION 0xF000 148*e65e175bSOded Gabbay #define mmSRAM_Y1_X0_BANK_BASE 0x7FFC220000ull 149*e65e175bSOded Gabbay #define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4 150*e65e175bSOded Gabbay #define SRAM_Y1_X0_BANK_SECTION 0x1000 151*e65e175bSOded Gabbay #define mmSRAM_Y1_X0_RTR_BASE 0x7FFC221000ull 152*e65e175bSOded Gabbay #define SRAM_Y1_X0_RTR_MAX_OFFSET 0x334 153*e65e175bSOded Gabbay #define SRAM_Y1_X0_RTR_SECTION 0x3000 154*e65e175bSOded Gabbay #define mmSRAM_Y1_X1_BANK_BASE 0x7FFC224000ull 155*e65e175bSOded Gabbay #define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4 156*e65e175bSOded Gabbay #define SRAM_Y1_X1_BANK_SECTION 0x1000 157*e65e175bSOded Gabbay #define mmSRAM_Y1_X1_RTR_BASE 0x7FFC225000ull 158*e65e175bSOded Gabbay #define SRAM_Y1_X1_RTR_MAX_OFFSET 0x334 159*e65e175bSOded Gabbay #define SRAM_Y1_X1_RTR_SECTION 0x3000 160*e65e175bSOded Gabbay #define mmSRAM_Y1_X2_BANK_BASE 0x7FFC228000ull 161*e65e175bSOded Gabbay #define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4 162*e65e175bSOded Gabbay #define SRAM_Y1_X2_BANK_SECTION 0x1000 163*e65e175bSOded Gabbay #define mmSRAM_Y1_X2_RTR_BASE 0x7FFC229000ull 164*e65e175bSOded Gabbay #define SRAM_Y1_X2_RTR_MAX_OFFSET 0x334 165*e65e175bSOded Gabbay #define SRAM_Y1_X2_RTR_SECTION 0x3000 166*e65e175bSOded Gabbay #define mmSRAM_Y1_X3_BANK_BASE 0x7FFC22C000ull 167*e65e175bSOded Gabbay #define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4 168*e65e175bSOded Gabbay #define SRAM_Y1_X3_BANK_SECTION 0x1000 169*e65e175bSOded Gabbay #define mmSRAM_Y1_X3_RTR_BASE 0x7FFC22D000ull 170*e65e175bSOded Gabbay #define SRAM_Y1_X3_RTR_MAX_OFFSET 0x334 171*e65e175bSOded Gabbay #define SRAM_Y1_X3_RTR_SECTION 0x3000 172*e65e175bSOded Gabbay #define mmSRAM_Y1_X4_BANK_BASE 0x7FFC230000ull 173*e65e175bSOded Gabbay #define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4 174*e65e175bSOded Gabbay #define SRAM_Y1_X4_BANK_SECTION 0x1000 175*e65e175bSOded Gabbay #define mmSRAM_Y1_X4_RTR_BASE 0x7FFC231000ull 176*e65e175bSOded Gabbay #define SRAM_Y1_X4_RTR_MAX_OFFSET 0x334 177*e65e175bSOded Gabbay #define SRAM_Y1_X4_RTR_SECTION 0xF000 178*e65e175bSOded Gabbay #define mmSRAM_Y2_X0_BANK_BASE 0x7FFC240000ull 179*e65e175bSOded Gabbay #define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4 180*e65e175bSOded Gabbay #define SRAM_Y2_X0_BANK_SECTION 0x1000 181*e65e175bSOded Gabbay #define mmSRAM_Y2_X0_RTR_BASE 0x7FFC241000ull 182*e65e175bSOded Gabbay #define SRAM_Y2_X0_RTR_MAX_OFFSET 0x334 183*e65e175bSOded Gabbay #define SRAM_Y2_X0_RTR_SECTION 0x3000 184*e65e175bSOded Gabbay #define mmSRAM_Y2_X1_BANK_BASE 0x7FFC244000ull 185*e65e175bSOded Gabbay #define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4 186*e65e175bSOded Gabbay #define SRAM_Y2_X1_BANK_SECTION 0x1000 187*e65e175bSOded Gabbay #define mmSRAM_Y2_X1_RTR_BASE 0x7FFC245000ull 188*e65e175bSOded Gabbay #define SRAM_Y2_X1_RTR_MAX_OFFSET 0x334 189*e65e175bSOded Gabbay #define SRAM_Y2_X1_RTR_SECTION 0x3000 190*e65e175bSOded Gabbay #define mmSRAM_Y2_X2_BANK_BASE 0x7FFC248000ull 191*e65e175bSOded Gabbay #define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4 192*e65e175bSOded Gabbay #define SRAM_Y2_X2_BANK_SECTION 0x1000 193*e65e175bSOded Gabbay #define mmSRAM_Y2_X2_RTR_BASE 0x7FFC249000ull 194*e65e175bSOded Gabbay #define SRAM_Y2_X2_RTR_MAX_OFFSET 0x334 195*e65e175bSOded Gabbay #define SRAM_Y2_X2_RTR_SECTION 0x3000 196*e65e175bSOded Gabbay #define mmSRAM_Y2_X3_BANK_BASE 0x7FFC24C000ull 197*e65e175bSOded Gabbay #define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4 198*e65e175bSOded Gabbay #define SRAM_Y2_X3_BANK_SECTION 0x1000 199*e65e175bSOded Gabbay #define mmSRAM_Y2_X3_RTR_BASE 0x7FFC24D000ull 200*e65e175bSOded Gabbay #define SRAM_Y2_X3_RTR_MAX_OFFSET 0x334 201*e65e175bSOded Gabbay #define SRAM_Y2_X3_RTR_SECTION 0x3000 202*e65e175bSOded Gabbay #define mmSRAM_Y2_X4_BANK_BASE 0x7FFC250000ull 203*e65e175bSOded Gabbay #define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4 204*e65e175bSOded Gabbay #define SRAM_Y2_X4_BANK_SECTION 0x1000 205*e65e175bSOded Gabbay #define mmSRAM_Y2_X4_RTR_BASE 0x7FFC251000ull 206*e65e175bSOded Gabbay #define SRAM_Y2_X4_RTR_MAX_OFFSET 0x334 207*e65e175bSOded Gabbay #define SRAM_Y2_X4_RTR_SECTION 0xF000 208*e65e175bSOded Gabbay #define mmSRAM_Y3_X0_BANK_BASE 0x7FFC260000ull 209*e65e175bSOded Gabbay #define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4 210*e65e175bSOded Gabbay #define SRAM_Y3_X0_BANK_SECTION 0x1000 211*e65e175bSOded Gabbay #define mmSRAM_Y3_X0_RTR_BASE 0x7FFC261000ull 212*e65e175bSOded Gabbay #define SRAM_Y3_X0_RTR_MAX_OFFSET 0x334 213*e65e175bSOded Gabbay #define SRAM_Y3_X0_RTR_SECTION 0x3000 214*e65e175bSOded Gabbay #define mmSRAM_Y3_X1_BANK_BASE 0x7FFC264000ull 215*e65e175bSOded Gabbay #define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4 216*e65e175bSOded Gabbay #define SRAM_Y3_X1_BANK_SECTION 0x1000 217*e65e175bSOded Gabbay #define mmSRAM_Y3_X1_RTR_BASE 0x7FFC265000ull 218*e65e175bSOded Gabbay #define SRAM_Y3_X1_RTR_MAX_OFFSET 0x334 219*e65e175bSOded Gabbay #define SRAM_Y3_X1_RTR_SECTION 0x3000 220*e65e175bSOded Gabbay #define mmSRAM_Y3_X2_BANK_BASE 0x7FFC268000ull 221*e65e175bSOded Gabbay #define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4 222*e65e175bSOded Gabbay #define SRAM_Y3_X2_BANK_SECTION 0x1000 223*e65e175bSOded Gabbay #define mmSRAM_Y3_X2_RTR_BASE 0x7FFC269000ull 224*e65e175bSOded Gabbay #define SRAM_Y3_X2_RTR_MAX_OFFSET 0x334 225*e65e175bSOded Gabbay #define SRAM_Y3_X2_RTR_SECTION 0x3000 226*e65e175bSOded Gabbay #define mmSRAM_Y3_X3_BANK_BASE 0x7FFC26C000ull 227*e65e175bSOded Gabbay #define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4 228*e65e175bSOded Gabbay #define SRAM_Y3_X3_BANK_SECTION 0x1000 229*e65e175bSOded Gabbay #define mmSRAM_Y3_X3_RTR_BASE 0x7FFC26D000ull 230*e65e175bSOded Gabbay #define SRAM_Y3_X3_RTR_MAX_OFFSET 0x334 231*e65e175bSOded Gabbay #define SRAM_Y3_X3_RTR_SECTION 0x3000 232*e65e175bSOded Gabbay #define mmSRAM_Y3_X4_BANK_BASE 0x7FFC270000ull 233*e65e175bSOded Gabbay #define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4 234*e65e175bSOded Gabbay #define SRAM_Y3_X4_BANK_SECTION 0x1000 235*e65e175bSOded Gabbay #define mmSRAM_Y3_X4_RTR_BASE 0x7FFC271000ull 236*e65e175bSOded Gabbay #define SRAM_Y3_X4_RTR_MAX_OFFSET 0x334 237*e65e175bSOded Gabbay #define SRAM_Y3_X4_RTR_SECTION 0xF000 238*e65e175bSOded Gabbay #define mmSRAM_Y4_X0_BANK_BASE 0x7FFC280000ull 239*e65e175bSOded Gabbay #define SRAM_Y4_X0_BANK_MAX_OFFSET 0x4 240*e65e175bSOded Gabbay #define SRAM_Y4_X0_BANK_SECTION 0x1000 241*e65e175bSOded Gabbay #define mmSRAM_Y4_X0_RTR_BASE 0x7FFC281000ull 242*e65e175bSOded Gabbay #define SRAM_Y4_X0_RTR_MAX_OFFSET 0x334 243*e65e175bSOded Gabbay #define SRAM_Y4_X0_RTR_SECTION 0x3000 244*e65e175bSOded Gabbay #define mmSRAM_Y4_X1_BANK_BASE 0x7FFC284000ull 245*e65e175bSOded Gabbay #define SRAM_Y4_X1_BANK_MAX_OFFSET 0x4 246*e65e175bSOded Gabbay #define SRAM_Y4_X1_BANK_SECTION 0x1000 247*e65e175bSOded Gabbay #define mmSRAM_Y4_X1_RTR_BASE 0x7FFC285000ull 248*e65e175bSOded Gabbay #define SRAM_Y4_X1_RTR_MAX_OFFSET 0x334 249*e65e175bSOded Gabbay #define SRAM_Y4_X1_RTR_SECTION 0x3000 250*e65e175bSOded Gabbay #define mmSRAM_Y4_X2_BANK_BASE 0x7FFC288000ull 251*e65e175bSOded Gabbay #define SRAM_Y4_X2_BANK_MAX_OFFSET 0x4 252*e65e175bSOded Gabbay #define SRAM_Y4_X2_BANK_SECTION 0x1000 253*e65e175bSOded Gabbay #define mmSRAM_Y4_X2_RTR_BASE 0x7FFC289000ull 254*e65e175bSOded Gabbay #define SRAM_Y4_X2_RTR_MAX_OFFSET 0x334 255*e65e175bSOded Gabbay #define SRAM_Y4_X2_RTR_SECTION 0x3000 256*e65e175bSOded Gabbay #define mmSRAM_Y4_X3_BANK_BASE 0x7FFC28C000ull 257*e65e175bSOded Gabbay #define SRAM_Y4_X3_BANK_MAX_OFFSET 0x4 258*e65e175bSOded Gabbay #define SRAM_Y4_X3_BANK_SECTION 0x1000 259*e65e175bSOded Gabbay #define mmSRAM_Y4_X3_RTR_BASE 0x7FFC28D000ull 260*e65e175bSOded Gabbay #define SRAM_Y4_X3_RTR_MAX_OFFSET 0x334 261*e65e175bSOded Gabbay #define SRAM_Y4_X3_RTR_SECTION 0x3000 262*e65e175bSOded Gabbay #define mmSRAM_Y4_X4_BANK_BASE 0x7FFC290000ull 263*e65e175bSOded Gabbay #define SRAM_Y4_X4_BANK_MAX_OFFSET 0x4 264*e65e175bSOded Gabbay #define SRAM_Y4_X4_BANK_SECTION 0x1000 265*e65e175bSOded Gabbay #define mmSRAM_Y4_X4_RTR_BASE 0x7FFC291000ull 266*e65e175bSOded Gabbay #define SRAM_Y4_X4_RTR_MAX_OFFSET 0x334 267*e65e175bSOded Gabbay #define SRAM_Y4_X4_RTR_SECTION 0xF000 268*e65e175bSOded Gabbay #define mmSRAM_Y5_X0_BANK_BASE 0x7FFC2A0000ull 269*e65e175bSOded Gabbay #define SRAM_Y5_X0_BANK_MAX_OFFSET 0x4 270*e65e175bSOded Gabbay #define SRAM_Y5_X0_BANK_SECTION 0x1000 271*e65e175bSOded Gabbay #define mmSRAM_Y5_X0_RTR_BASE 0x7FFC2A1000ull 272*e65e175bSOded Gabbay #define SRAM_Y5_X0_RTR_MAX_OFFSET 0x334 273*e65e175bSOded Gabbay #define SRAM_Y5_X0_RTR_SECTION 0x3000 274*e65e175bSOded Gabbay #define mmSRAM_Y5_X1_BANK_BASE 0x7FFC2A4000ull 275*e65e175bSOded Gabbay #define SRAM_Y5_X1_BANK_MAX_OFFSET 0x4 276*e65e175bSOded Gabbay #define SRAM_Y5_X1_BANK_SECTION 0x1000 277*e65e175bSOded Gabbay #define mmSRAM_Y5_X1_RTR_BASE 0x7FFC2A5000ull 278*e65e175bSOded Gabbay #define SRAM_Y5_X1_RTR_MAX_OFFSET 0x334 279*e65e175bSOded Gabbay #define SRAM_Y5_X1_RTR_SECTION 0x3000 280*e65e175bSOded Gabbay #define mmSRAM_Y5_X2_BANK_BASE 0x7FFC2A8000ull 281*e65e175bSOded Gabbay #define SRAM_Y5_X2_BANK_MAX_OFFSET 0x4 282*e65e175bSOded Gabbay #define SRAM_Y5_X2_BANK_SECTION 0x1000 283*e65e175bSOded Gabbay #define mmSRAM_Y5_X2_RTR_BASE 0x7FFC2A9000ull 284*e65e175bSOded Gabbay #define SRAM_Y5_X2_RTR_MAX_OFFSET 0x334 285*e65e175bSOded Gabbay #define SRAM_Y5_X2_RTR_SECTION 0x3000 286*e65e175bSOded Gabbay #define mmSRAM_Y5_X3_BANK_BASE 0x7FFC2AC000ull 287*e65e175bSOded Gabbay #define SRAM_Y5_X3_BANK_MAX_OFFSET 0x4 288*e65e175bSOded Gabbay #define SRAM_Y5_X3_BANK_SECTION 0x1000 289*e65e175bSOded Gabbay #define mmSRAM_Y5_X3_RTR_BASE 0x7FFC2AD000ull 290*e65e175bSOded Gabbay #define SRAM_Y5_X3_RTR_MAX_OFFSET 0x334 291*e65e175bSOded Gabbay #define SRAM_Y5_X3_RTR_SECTION 0x3000 292*e65e175bSOded Gabbay #define mmSRAM_Y5_X4_BANK_BASE 0x7FFC2B0000ull 293*e65e175bSOded Gabbay #define SRAM_Y5_X4_BANK_MAX_OFFSET 0x4 294*e65e175bSOded Gabbay #define SRAM_Y5_X4_BANK_SECTION 0x1000 295*e65e175bSOded Gabbay #define mmSRAM_Y5_X4_RTR_BASE 0x7FFC2B1000ull 296*e65e175bSOded Gabbay #define SRAM_Y5_X4_RTR_MAX_OFFSET 0x334 297*e65e175bSOded Gabbay #define SRAM_Y5_X4_RTR_SECTION 0x14F000 298*e65e175bSOded Gabbay #define mmDMA_QM_0_BASE 0x7FFC400000ull 299*e65e175bSOded Gabbay #define DMA_QM_0_MAX_OFFSET 0x310 300*e65e175bSOded Gabbay #define DMA_QM_0_SECTION 0x1000 301*e65e175bSOded Gabbay #define mmDMA_CH_0_BASE 0x7FFC401000ull 302*e65e175bSOded Gabbay #define DMA_CH_0_MAX_OFFSET 0x200 303*e65e175bSOded Gabbay #define DMA_CH_0_SECTION 0x7000 304*e65e175bSOded Gabbay #define mmDMA_QM_1_BASE 0x7FFC408000ull 305*e65e175bSOded Gabbay #define DMA_QM_1_MAX_OFFSET 0x310 306*e65e175bSOded Gabbay #define DMA_QM_1_SECTION 0x1000 307*e65e175bSOded Gabbay #define mmDMA_CH_1_BASE 0x7FFC409000ull 308*e65e175bSOded Gabbay #define DMA_CH_1_MAX_OFFSET 0x200 309*e65e175bSOded Gabbay #define DMA_CH_1_SECTION 0x7000 310*e65e175bSOded Gabbay #define mmDMA_QM_2_BASE 0x7FFC410000ull 311*e65e175bSOded Gabbay #define DMA_QM_2_MAX_OFFSET 0x310 312*e65e175bSOded Gabbay #define DMA_QM_2_SECTION 0x1000 313*e65e175bSOded Gabbay #define mmDMA_CH_2_BASE 0x7FFC411000ull 314*e65e175bSOded Gabbay #define DMA_CH_2_MAX_OFFSET 0x200 315*e65e175bSOded Gabbay #define DMA_CH_2_SECTION 0x7000 316*e65e175bSOded Gabbay #define mmDMA_QM_3_BASE 0x7FFC418000ull 317*e65e175bSOded Gabbay #define DMA_QM_3_MAX_OFFSET 0x310 318*e65e175bSOded Gabbay #define DMA_QM_3_SECTION 0x1000 319*e65e175bSOded Gabbay #define mmDMA_CH_3_BASE 0x7FFC419000ull 320*e65e175bSOded Gabbay #define DMA_CH_3_MAX_OFFSET 0x200 321*e65e175bSOded Gabbay #define DMA_CH_3_SECTION 0x7000 322*e65e175bSOded Gabbay #define mmDMA_QM_4_BASE 0x7FFC420000ull 323*e65e175bSOded Gabbay #define DMA_QM_4_MAX_OFFSET 0x310 324*e65e175bSOded Gabbay #define DMA_QM_4_SECTION 0x1000 325*e65e175bSOded Gabbay #define mmDMA_CH_4_BASE 0x7FFC421000ull 326*e65e175bSOded Gabbay #define DMA_CH_4_MAX_OFFSET 0x200 327*e65e175bSOded Gabbay #define DMA_CH_4_SECTION 0x20000 328*e65e175bSOded Gabbay #define mmCPU_CA53_CFG_BASE 0x7FFC441000ull 329*e65e175bSOded Gabbay #define CPU_CA53_CFG_MAX_OFFSET 0x218 330*e65e175bSOded Gabbay #define CPU_CA53_CFG_SECTION 0x1000 331*e65e175bSOded Gabbay #define mmCPU_IF_BASE 0x7FFC442000ull 332*e65e175bSOded Gabbay #define CPU_IF_MAX_OFFSET 0x134 333*e65e175bSOded Gabbay #define CPU_IF_SECTION 0x2000 334*e65e175bSOded Gabbay #define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull 335*e65e175bSOded Gabbay #define CPU_TIMESTAMP_MAX_OFFSET 0x1000 336*e65e175bSOded Gabbay #define CPU_TIMESTAMP_SECTION 0x3C000 337*e65e175bSOded Gabbay #define mmMMU_BASE 0x7FFC480000ull 338*e65e175bSOded Gabbay #define MMU_MAX_OFFSET 0x44 339*e65e175bSOded Gabbay #define MMU_SECTION 0x10000 340*e65e175bSOded Gabbay #define mmSTLB_BASE 0x7FFC490000ull 341*e65e175bSOded Gabbay #define STLB_MAX_OFFSET 0x50 342*e65e175bSOded Gabbay #define STLB_SECTION 0x10000 343*e65e175bSOded Gabbay #define mmNORTH_THERMAL_SENSOR_BASE 0x7FFC4A0000ull 344*e65e175bSOded Gabbay #define NORTH_THERMAL_SENSOR_MAX_OFFSET 0xE64 345*e65e175bSOded Gabbay #define NORTH_THERMAL_SENSOR_SECTION 0x1000 346*e65e175bSOded Gabbay #define mmMC_PLL_BASE 0x7FFC4A1000ull 347*e65e175bSOded Gabbay #define MC_PLL_MAX_OFFSET 0x444 348*e65e175bSOded Gabbay #define MC_PLL_SECTION 0x1000 349*e65e175bSOded Gabbay #define mmCPU_PLL_BASE 0x7FFC4A2000ull 350*e65e175bSOded Gabbay #define CPU_PLL_MAX_OFFSET 0x444 351*e65e175bSOded Gabbay #define CPU_PLL_SECTION 0x1000 352*e65e175bSOded Gabbay #define mmIC_PLL_BASE 0x7FFC4A3000ull 353*e65e175bSOded Gabbay #define IC_PLL_MAX_OFFSET 0x444 354*e65e175bSOded Gabbay #define IC_PLL_SECTION 0x1000 355*e65e175bSOded Gabbay #define mmDMA_PROCESS_MON_BASE 0x7FFC4A4000ull 356*e65e175bSOded Gabbay #define DMA_PROCESS_MON_MAX_OFFSET 0x4 357*e65e175bSOded Gabbay #define DMA_PROCESS_MON_SECTION 0xC000 358*e65e175bSOded Gabbay #define mmDMA_MACRO_BASE 0x7FFC4B0000ull 359*e65e175bSOded Gabbay #define DMA_MACRO_MAX_OFFSET 0x15C 360*e65e175bSOded Gabbay #define DMA_MACRO_SECTION 0x150000 361*e65e175bSOded Gabbay #define mmDDR_PHY_CH0_BASE 0x7FFC600000ull 362*e65e175bSOded Gabbay #define DDR_PHY_CH0_MAX_OFFSET 0x0 363*e65e175bSOded Gabbay #define DDR_PHY_CH0_SECTION 0x40000 364*e65e175bSOded Gabbay #define mmDDR_MC_CH0_BASE 0x7FFC640000ull 365*e65e175bSOded Gabbay #define DDR_MC_CH0_MAX_OFFSET 0xF34 366*e65e175bSOded Gabbay #define DDR_MC_CH0_SECTION 0x8000 367*e65e175bSOded Gabbay #define mmDDR_MISC_CH0_BASE 0x7FFC648000ull 368*e65e175bSOded Gabbay #define DDR_MISC_CH0_MAX_OFFSET 0x204 369*e65e175bSOded Gabbay #define DDR_MISC_CH0_SECTION 0xB8000 370*e65e175bSOded Gabbay #define mmDDR_PHY_CH1_BASE 0x7FFC700000ull 371*e65e175bSOded Gabbay #define DDR_PHY_CH1_MAX_OFFSET 0x0 372*e65e175bSOded Gabbay #define DDR_PHY_CH1_SECTION 0x40000 373*e65e175bSOded Gabbay #define mmDDR_MC_CH1_BASE 0x7FFC740000ull 374*e65e175bSOded Gabbay #define DDR_MC_CH1_MAX_OFFSET 0xF34 375*e65e175bSOded Gabbay #define DDR_MC_CH1_SECTION 0x8000 376*e65e175bSOded Gabbay #define mmDDR_MISC_CH1_BASE 0x7FFC748000ull 377*e65e175bSOded Gabbay #define DDR_MISC_CH1_MAX_OFFSET 0x204 378*e65e175bSOded Gabbay #define DDR_MISC_CH1_SECTION 0xB8000 379*e65e175bSOded Gabbay #define mmGIC_BASE 0x7FFC800000ull 380*e65e175bSOded Gabbay #define GIC_MAX_OFFSET 0x10000 381*e65e175bSOded Gabbay #define GIC_SECTION 0x401000 382*e65e175bSOded Gabbay #define mmPCIE_WRAP_BASE 0x7FFCC01000ull 383*e65e175bSOded Gabbay #define PCIE_WRAP_MAX_OFFSET 0xDF4 384*e65e175bSOded Gabbay #define PCIE_WRAP_SECTION 0x1000 385*e65e175bSOded Gabbay #define mmPCIE_DBI_BASE 0x7FFCC02000ull 386*e65e175bSOded Gabbay #define PCIE_DBI_MAX_OFFSET 0xC04 387*e65e175bSOded Gabbay #define PCIE_DBI_SECTION 0x2000 388*e65e175bSOded Gabbay #define mmPCIE_CORE_BASE 0x7FFCC04000ull 389*e65e175bSOded Gabbay #define PCIE_CORE_MAX_OFFSET 0x9B8 390*e65e175bSOded Gabbay #define PCIE_CORE_SECTION 0x1000 391*e65e175bSOded Gabbay #define mmPCIE_DB_CFG_BASE 0x7FFCC05000ull 392*e65e175bSOded Gabbay #define PCIE_DB_CFG_MAX_OFFSET 0xE34 393*e65e175bSOded Gabbay #define PCIE_DB_CFG_SECTION 0x1000 394*e65e175bSOded Gabbay #define mmPCIE_DB_CMD_BASE 0x7FFCC06000ull 395*e65e175bSOded Gabbay #define PCIE_DB_CMD_MAX_OFFSET 0x810 396*e65e175bSOded Gabbay #define PCIE_DB_CMD_SECTION 0x1000 397*e65e175bSOded Gabbay #define mmPCIE_AUX_BASE 0x7FFCC07000ull 398*e65e175bSOded Gabbay #define PCIE_AUX_MAX_OFFSET 0x9BC 399*e65e175bSOded Gabbay #define PCIE_AUX_SECTION 0x1000 400*e65e175bSOded Gabbay #define mmPCIE_DB_RSV_BASE 0x7FFCC08000ull 401*e65e175bSOded Gabbay #define PCIE_DB_RSV_MAX_OFFSET 0x800 402*e65e175bSOded Gabbay #define PCIE_DB_RSV_SECTION 0x8000 403*e65e175bSOded Gabbay #define mmPCIE_PHY_BASE 0x7FFCC10000ull 404*e65e175bSOded Gabbay #define PCIE_PHY_MAX_OFFSET 0x924 405*e65e175bSOded Gabbay #define PCIE_PHY_SECTION 0x30000 406*e65e175bSOded Gabbay #define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull 407*e65e175bSOded Gabbay #define PSOC_I2C_M0_MAX_OFFSET 0x100 408*e65e175bSOded Gabbay #define PSOC_I2C_M0_SECTION 0x1000 409*e65e175bSOded Gabbay #define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull 410*e65e175bSOded Gabbay #define PSOC_I2C_M1_MAX_OFFSET 0x100 411*e65e175bSOded Gabbay #define PSOC_I2C_M1_SECTION 0x1000 412*e65e175bSOded Gabbay #define mmPSOC_I2C_S_BASE 0x7FFCC42000ull 413*e65e175bSOded Gabbay #define PSOC_I2C_S_MAX_OFFSET 0x100 414*e65e175bSOded Gabbay #define PSOC_I2C_S_SECTION 0x1000 415*e65e175bSOded Gabbay #define mmPSOC_SPI_BASE 0x7FFCC43000ull 416*e65e175bSOded Gabbay #define PSOC_SPI_MAX_OFFSET 0x100 417*e65e175bSOded Gabbay #define PSOC_SPI_SECTION 0x1000 418*e65e175bSOded Gabbay #define mmPSOC_EMMC_BASE 0x7FFCC44000ull 419*e65e175bSOded Gabbay #define PSOC_EMMC_MAX_OFFSET 0xF70 420*e65e175bSOded Gabbay #define PSOC_EMMC_SECTION 0x1000 421*e65e175bSOded Gabbay #define mmPSOC_UART_0_BASE 0x7FFCC45000ull 422*e65e175bSOded Gabbay #define PSOC_UART_0_MAX_OFFSET 0x1000 423*e65e175bSOded Gabbay #define PSOC_UART_0_SECTION 0x1000 424*e65e175bSOded Gabbay #define mmPSOC_UART_1_BASE 0x7FFCC46000ull 425*e65e175bSOded Gabbay #define PSOC_UART_1_MAX_OFFSET 0x1000 426*e65e175bSOded Gabbay #define PSOC_UART_1_SECTION 0x1000 427*e65e175bSOded Gabbay #define mmPSOC_TIMER_BASE 0x7FFCC47000ull 428*e65e175bSOded Gabbay #define PSOC_TIMER_MAX_OFFSET 0x1000 429*e65e175bSOded Gabbay #define PSOC_TIMER_SECTION 0x1000 430*e65e175bSOded Gabbay #define mmPSOC_WDOG_BASE 0x7FFCC48000ull 431*e65e175bSOded Gabbay #define PSOC_WDOG_MAX_OFFSET 0x1000 432*e65e175bSOded Gabbay #define PSOC_WDOG_SECTION 0x1000 433*e65e175bSOded Gabbay #define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull 434*e65e175bSOded Gabbay #define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 435*e65e175bSOded Gabbay #define PSOC_TIMESTAMP_SECTION 0x1000 436*e65e175bSOded Gabbay #define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull 437*e65e175bSOded Gabbay #define PSOC_EFUSE_MAX_OFFSET 0x10C 438*e65e175bSOded Gabbay #define PSOC_EFUSE_SECTION 0x1000 439*e65e175bSOded Gabbay #define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull 440*e65e175bSOded Gabbay #define PSOC_GLOBAL_CONF_MAX_OFFSET 0xA48 441*e65e175bSOded Gabbay #define PSOC_GLOBAL_CONF_SECTION 0x1000 442*e65e175bSOded Gabbay #define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull 443*e65e175bSOded Gabbay #define PSOC_GPIO0_MAX_OFFSET 0x1000 444*e65e175bSOded Gabbay #define PSOC_GPIO0_SECTION 0x1000 445*e65e175bSOded Gabbay #define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull 446*e65e175bSOded Gabbay #define PSOC_GPIO1_MAX_OFFSET 0x1000 447*e65e175bSOded Gabbay #define PSOC_GPIO1_SECTION 0x1000 448*e65e175bSOded Gabbay #define mmPSOC_BTL_BASE 0x7FFCC4E000ull 449*e65e175bSOded Gabbay #define PSOC_BTL_MAX_OFFSET 0x124 450*e65e175bSOded Gabbay #define PSOC_BTL_SECTION 0x1000 451*e65e175bSOded Gabbay #define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull 452*e65e175bSOded Gabbay #define PSOC_CS_TRACE_MAX_OFFSET 0x0 453*e65e175bSOded Gabbay #define PSOC_CS_TRACE_SECTION 0x1000 454*e65e175bSOded Gabbay #define mmPSOC_GPIO2_BASE 0x7FFCC50000ull 455*e65e175bSOded Gabbay #define PSOC_GPIO2_MAX_OFFSET 0x1000 456*e65e175bSOded Gabbay #define PSOC_GPIO2_SECTION 0x1000 457*e65e175bSOded Gabbay #define mmPSOC_GPIO3_BASE 0x7FFCC51000ull 458*e65e175bSOded Gabbay #define PSOC_GPIO3_MAX_OFFSET 0x1000 459*e65e175bSOded Gabbay #define PSOC_GPIO3_SECTION 0x1000 460*e65e175bSOded Gabbay #define mmPSOC_GPIO4_BASE 0x7FFCC52000ull 461*e65e175bSOded Gabbay #define PSOC_GPIO4_MAX_OFFSET 0x1000 462*e65e175bSOded Gabbay #define PSOC_GPIO4_SECTION 0x1000 463*e65e175bSOded Gabbay #define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull 464*e65e175bSOded Gabbay #define PSOC_DFT_EFUSE_MAX_OFFSET 0x10C 465*e65e175bSOded Gabbay #define PSOC_DFT_EFUSE_SECTION 0x1000 466*e65e175bSOded Gabbay #define mmPSOC_PM_BASE 0x7FFCC54000ull 467*e65e175bSOded Gabbay #define PSOC_PM_MAX_OFFSET 0x4 468*e65e175bSOded Gabbay #define PSOC_PM_SECTION 0x1000 469*e65e175bSOded Gabbay #define mmPSOC_TS_BASE 0x7FFCC55000ull 470*e65e175bSOded Gabbay #define PSOC_TS_MAX_OFFSET 0xE64 471*e65e175bSOded Gabbay #define PSOC_TS_SECTION 0xB000 472*e65e175bSOded Gabbay #define mmPSOC_MII_BASE 0x7FFCC60000ull 473*e65e175bSOded Gabbay #define PSOC_MII_MAX_OFFSET 0x105C 474*e65e175bSOded Gabbay #define PSOC_MII_SECTION 0x10000 475*e65e175bSOded Gabbay #define mmPSOC_EMMC_PLL_BASE 0x7FFCC70000ull 476*e65e175bSOded Gabbay #define PSOC_EMMC_PLL_MAX_OFFSET 0x444 477*e65e175bSOded Gabbay #define PSOC_EMMC_PLL_SECTION 0x1000 478*e65e175bSOded Gabbay #define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull 479*e65e175bSOded Gabbay #define PSOC_MME_PLL_MAX_OFFSET 0x444 480*e65e175bSOded Gabbay #define PSOC_MME_PLL_SECTION 0x1000 481*e65e175bSOded Gabbay #define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull 482*e65e175bSOded Gabbay #define PSOC_PCI_PLL_MAX_OFFSET 0x444 483*e65e175bSOded Gabbay #define PSOC_PCI_PLL_SECTION 0x6000 484*e65e175bSOded Gabbay #define mmPSOC_PWM0_BASE 0x7FFCC78000ull 485*e65e175bSOded Gabbay #define PSOC_PWM0_MAX_OFFSET 0x58 486*e65e175bSOded Gabbay #define PSOC_PWM0_SECTION 0x1000 487*e65e175bSOded Gabbay #define mmPSOC_PWM1_BASE 0x7FFCC79000ull 488*e65e175bSOded Gabbay #define PSOC_PWM1_MAX_OFFSET 0x58 489*e65e175bSOded Gabbay #define PSOC_PWM1_SECTION 0x1000 490*e65e175bSOded Gabbay #define mmPSOC_PWM2_BASE 0x7FFCC7A000ull 491*e65e175bSOded Gabbay #define PSOC_PWM2_MAX_OFFSET 0x58 492*e65e175bSOded Gabbay #define PSOC_PWM2_SECTION 0x1000 493*e65e175bSOded Gabbay #define mmPSOC_PWM3_BASE 0x7FFCC7B000ull 494*e65e175bSOded Gabbay #define PSOC_PWM3_MAX_OFFSET 0x58 495*e65e175bSOded Gabbay #define PSOC_PWM3_SECTION 0x185000 496*e65e175bSOded Gabbay #define mmTPC0_NRTR_BASE 0x7FFCE00000ull 497*e65e175bSOded Gabbay #define TPC0_NRTR_MAX_OFFSET 0x608 498*e65e175bSOded Gabbay #define TPC0_NRTR_SECTION 0x1000 499*e65e175bSOded Gabbay #define mmTPC_PLL_BASE 0x7FFCE01000ull 500*e65e175bSOded Gabbay #define TPC_PLL_MAX_OFFSET 0x444 501*e65e175bSOded Gabbay #define TPC_PLL_SECTION 0x1000 502*e65e175bSOded Gabbay #define mmTPC_THEMAL_SENSOR_BASE 0x7FFCE02000ull 503*e65e175bSOded Gabbay #define TPC_THEMAL_SENSOR_MAX_OFFSET 0xE64 504*e65e175bSOded Gabbay #define TPC_THEMAL_SENSOR_SECTION 0x1000 505*e65e175bSOded Gabbay #define mmTPC_PROCESS_MON_BASE 0x7FFCE03000ull 506*e65e175bSOded Gabbay #define TPC_PROCESS_MON_MAX_OFFSET 0x4 507*e65e175bSOded Gabbay #define TPC_PROCESS_MON_SECTION 0x1000 508*e65e175bSOded Gabbay #define mmTPC0_RD_REGULATOR_BASE 0x7FFCE04000ull 509*e65e175bSOded Gabbay #define TPC0_RD_REGULATOR_MAX_OFFSET 0x74 510*e65e175bSOded Gabbay #define TPC0_RD_REGULATOR_SECTION 0x1000 511*e65e175bSOded Gabbay #define mmTPC0_WR_REGULATOR_BASE 0x7FFCE05000ull 512*e65e175bSOded Gabbay #define TPC0_WR_REGULATOR_MAX_OFFSET 0x74 513*e65e175bSOded Gabbay #define TPC0_WR_REGULATOR_SECTION 0x1000 514*e65e175bSOded Gabbay #define mmTPC0_CFG_BASE 0x7FFCE06000ull 515*e65e175bSOded Gabbay #define TPC0_CFG_MAX_OFFSET 0xE30 516*e65e175bSOded Gabbay #define TPC0_CFG_SECTION 0x2000 517*e65e175bSOded Gabbay #define mmTPC0_QM_BASE 0x7FFCE08000ull 518*e65e175bSOded Gabbay #define TPC0_QM_MAX_OFFSET 0x310 519*e65e175bSOded Gabbay #define TPC0_QM_SECTION 0x1000 520*e65e175bSOded Gabbay #define mmTPC0_CMDQ_BASE 0x7FFCE09000ull 521*e65e175bSOded Gabbay #define TPC0_CMDQ_MAX_OFFSET 0x310 522*e65e175bSOded Gabbay #define TPC0_CMDQ_SECTION 0x37000 523*e65e175bSOded Gabbay #define mmTPC1_RTR_BASE 0x7FFCE40000ull 524*e65e175bSOded Gabbay #define TPC1_RTR_MAX_OFFSET 0x608 525*e65e175bSOded Gabbay #define TPC1_RTR_SECTION 0x4000 526*e65e175bSOded Gabbay #define mmTPC1_WR_REGULATOR_BASE 0x7FFCE44000ull 527*e65e175bSOded Gabbay #define TPC1_WR_REGULATOR_MAX_OFFSET 0x74 528*e65e175bSOded Gabbay #define TPC1_WR_REGULATOR_SECTION 0x1000 529*e65e175bSOded Gabbay #define mmTPC1_RD_REGULATOR_BASE 0x7FFCE45000ull 530*e65e175bSOded Gabbay #define TPC1_RD_REGULATOR_MAX_OFFSET 0x74 531*e65e175bSOded Gabbay #define TPC1_RD_REGULATOR_SECTION 0x1000 532*e65e175bSOded Gabbay #define mmTPC1_CFG_BASE 0x7FFCE46000ull 533*e65e175bSOded Gabbay #define TPC1_CFG_MAX_OFFSET 0xE30 534*e65e175bSOded Gabbay #define TPC1_CFG_SECTION 0x2000 535*e65e175bSOded Gabbay #define mmTPC1_QM_BASE 0x7FFCE48000ull 536*e65e175bSOded Gabbay #define TPC1_QM_MAX_OFFSET 0x310 537*e65e175bSOded Gabbay #define TPC1_QM_SECTION 0x1000 538*e65e175bSOded Gabbay #define mmTPC1_CMDQ_BASE 0x7FFCE49000ull 539*e65e175bSOded Gabbay #define TPC1_CMDQ_MAX_OFFSET 0x310 540*e65e175bSOded Gabbay #define TPC1_CMDQ_SECTION 0x37000 541*e65e175bSOded Gabbay #define mmTPC2_RTR_BASE 0x7FFCE80000ull 542*e65e175bSOded Gabbay #define TPC2_RTR_MAX_OFFSET 0x608 543*e65e175bSOded Gabbay #define TPC2_RTR_SECTION 0x4000 544*e65e175bSOded Gabbay #define mmTPC2_RD_REGULATOR_BASE 0x7FFCE84000ull 545*e65e175bSOded Gabbay #define TPC2_RD_REGULATOR_MAX_OFFSET 0x74 546*e65e175bSOded Gabbay #define TPC2_RD_REGULATOR_SECTION 0x1000 547*e65e175bSOded Gabbay #define mmTPC2_WR_REGULATOR_BASE 0x7FFCE85000ull 548*e65e175bSOded Gabbay #define TPC2_WR_REGULATOR_MAX_OFFSET 0x74 549*e65e175bSOded Gabbay #define TPC2_WR_REGULATOR_SECTION 0x1000 550*e65e175bSOded Gabbay #define mmTPC2_CFG_BASE 0x7FFCE86000ull 551*e65e175bSOded Gabbay #define TPC2_CFG_MAX_OFFSET 0xE30 552*e65e175bSOded Gabbay #define TPC2_CFG_SECTION 0x2000 553*e65e175bSOded Gabbay #define mmTPC2_QM_BASE 0x7FFCE88000ull 554*e65e175bSOded Gabbay #define TPC2_QM_MAX_OFFSET 0x310 555*e65e175bSOded Gabbay #define TPC2_QM_SECTION 0x1000 556*e65e175bSOded Gabbay #define mmTPC2_CMDQ_BASE 0x7FFCE89000ull 557*e65e175bSOded Gabbay #define TPC2_CMDQ_MAX_OFFSET 0x310 558*e65e175bSOded Gabbay #define TPC2_CMDQ_SECTION 0x37000 559*e65e175bSOded Gabbay #define mmTPC3_RTR_BASE 0x7FFCEC0000ull 560*e65e175bSOded Gabbay #define TPC3_RTR_MAX_OFFSET 0x608 561*e65e175bSOded Gabbay #define TPC3_RTR_SECTION 0x4000 562*e65e175bSOded Gabbay #define mmTPC3_RD_REGULATOR_BASE 0x7FFCEC4000ull 563*e65e175bSOded Gabbay #define TPC3_RD_REGULATOR_MAX_OFFSET 0x74 564*e65e175bSOded Gabbay #define TPC3_RD_REGULATOR_SECTION 0x1000 565*e65e175bSOded Gabbay #define mmTPC3_WR_REGULATOR_BASE 0x7FFCEC5000ull 566*e65e175bSOded Gabbay #define TPC3_WR_REGULATOR_MAX_OFFSET 0x74 567*e65e175bSOded Gabbay #define TPC3_WR_REGULATOR_SECTION 0x1000 568*e65e175bSOded Gabbay #define mmTPC3_CFG_BASE 0x7FFCEC6000ull 569*e65e175bSOded Gabbay #define TPC3_CFG_MAX_OFFSET 0xE30 570*e65e175bSOded Gabbay #define TPC3_CFG_SECTION 0x2000 571*e65e175bSOded Gabbay #define mmTPC3_QM_BASE 0x7FFCEC8000ull 572*e65e175bSOded Gabbay #define TPC3_QM_MAX_OFFSET 0x310 573*e65e175bSOded Gabbay #define TPC3_QM_SECTION 0x1000 574*e65e175bSOded Gabbay #define mmTPC3_CMDQ_BASE 0x7FFCEC9000ull 575*e65e175bSOded Gabbay #define TPC3_CMDQ_MAX_OFFSET 0x310 576*e65e175bSOded Gabbay #define TPC3_CMDQ_SECTION 0x37000 577*e65e175bSOded Gabbay #define mmTPC4_RTR_BASE 0x7FFCF00000ull 578*e65e175bSOded Gabbay #define TPC4_RTR_MAX_OFFSET 0x608 579*e65e175bSOded Gabbay #define TPC4_RTR_SECTION 0x4000 580*e65e175bSOded Gabbay #define mmTPC4_RD_REGULATOR_BASE 0x7FFCF04000ull 581*e65e175bSOded Gabbay #define TPC4_RD_REGULATOR_MAX_OFFSET 0x74 582*e65e175bSOded Gabbay #define TPC4_RD_REGULATOR_SECTION 0x1000 583*e65e175bSOded Gabbay #define mmTPC4_WR_REGULATOR_BASE 0x7FFCF05000ull 584*e65e175bSOded Gabbay #define TPC4_WR_REGULATOR_MAX_OFFSET 0x74 585*e65e175bSOded Gabbay #define TPC4_WR_REGULATOR_SECTION 0x1000 586*e65e175bSOded Gabbay #define mmTPC4_CFG_BASE 0x7FFCF06000ull 587*e65e175bSOded Gabbay #define TPC4_CFG_MAX_OFFSET 0xE30 588*e65e175bSOded Gabbay #define TPC4_CFG_SECTION 0x2000 589*e65e175bSOded Gabbay #define mmTPC4_QM_BASE 0x7FFCF08000ull 590*e65e175bSOded Gabbay #define TPC4_QM_MAX_OFFSET 0x310 591*e65e175bSOded Gabbay #define TPC4_QM_SECTION 0x1000 592*e65e175bSOded Gabbay #define mmTPC4_CMDQ_BASE 0x7FFCF09000ull 593*e65e175bSOded Gabbay #define TPC4_CMDQ_MAX_OFFSET 0x310 594*e65e175bSOded Gabbay #define TPC4_CMDQ_SECTION 0x37000 595*e65e175bSOded Gabbay #define mmTPC5_RTR_BASE 0x7FFCF40000ull 596*e65e175bSOded Gabbay #define TPC5_RTR_MAX_OFFSET 0x608 597*e65e175bSOded Gabbay #define TPC5_RTR_SECTION 0x4000 598*e65e175bSOded Gabbay #define mmTPC5_RD_REGULATOR_BASE 0x7FFCF44000ull 599*e65e175bSOded Gabbay #define TPC5_RD_REGULATOR_MAX_OFFSET 0x74 600*e65e175bSOded Gabbay #define TPC5_RD_REGULATOR_SECTION 0x1000 601*e65e175bSOded Gabbay #define mmTPC5_WR_REGULATOR_BASE 0x7FFCF45000ull 602*e65e175bSOded Gabbay #define TPC5_WR_REGULATOR_MAX_OFFSET 0x74 603*e65e175bSOded Gabbay #define TPC5_WR_REGULATOR_SECTION 0x1000 604*e65e175bSOded Gabbay #define mmTPC5_CFG_BASE 0x7FFCF46000ull 605*e65e175bSOded Gabbay #define TPC5_CFG_MAX_OFFSET 0xE30 606*e65e175bSOded Gabbay #define TPC5_CFG_SECTION 0x2000 607*e65e175bSOded Gabbay #define mmTPC5_QM_BASE 0x7FFCF48000ull 608*e65e175bSOded Gabbay #define TPC5_QM_MAX_OFFSET 0x310 609*e65e175bSOded Gabbay #define TPC5_QM_SECTION 0x1000 610*e65e175bSOded Gabbay #define mmTPC5_CMDQ_BASE 0x7FFCF49000ull 611*e65e175bSOded Gabbay #define TPC5_CMDQ_MAX_OFFSET 0x310 612*e65e175bSOded Gabbay #define TPC5_CMDQ_SECTION 0x37000 613*e65e175bSOded Gabbay #define mmTPC6_RTR_BASE 0x7FFCF80000ull 614*e65e175bSOded Gabbay #define TPC6_RTR_MAX_OFFSET 0x608 615*e65e175bSOded Gabbay #define TPC6_RTR_SECTION 0x4000 616*e65e175bSOded Gabbay #define mmTPC6_RD_REGULATOR_BASE 0x7FFCF84000ull 617*e65e175bSOded Gabbay #define TPC6_RD_REGULATOR_MAX_OFFSET 0x74 618*e65e175bSOded Gabbay #define TPC6_RD_REGULATOR_SECTION 0x1000 619*e65e175bSOded Gabbay #define mmTPC6_WR_REGULATOR_BASE 0x7FFCF85000ull 620*e65e175bSOded Gabbay #define TPC6_WR_REGULATOR_MAX_OFFSET 0x74 621*e65e175bSOded Gabbay #define TPC6_WR_REGULATOR_SECTION 0x1000 622*e65e175bSOded Gabbay #define mmTPC6_CFG_BASE 0x7FFCF86000ull 623*e65e175bSOded Gabbay #define TPC6_CFG_MAX_OFFSET 0xE30 624*e65e175bSOded Gabbay #define TPC6_CFG_SECTION 0x2000 625*e65e175bSOded Gabbay #define mmTPC6_QM_BASE 0x7FFCF88000ull 626*e65e175bSOded Gabbay #define TPC6_QM_MAX_OFFSET 0x310 627*e65e175bSOded Gabbay #define TPC6_QM_SECTION 0x1000 628*e65e175bSOded Gabbay #define mmTPC6_CMDQ_BASE 0x7FFCF89000ull 629*e65e175bSOded Gabbay #define TPC6_CMDQ_MAX_OFFSET 0x310 630*e65e175bSOded Gabbay #define TPC6_CMDQ_SECTION 0x37000 631*e65e175bSOded Gabbay #define mmTPC7_NRTR_BASE 0x7FFCFC0000ull 632*e65e175bSOded Gabbay #define TPC7_NRTR_MAX_OFFSET 0x608 633*e65e175bSOded Gabbay #define TPC7_NRTR_SECTION 0x4000 634*e65e175bSOded Gabbay #define mmTPC7_RD_REGULATOR_BASE 0x7FFCFC4000ull 635*e65e175bSOded Gabbay #define TPC7_RD_REGULATOR_MAX_OFFSET 0x74 636*e65e175bSOded Gabbay #define TPC7_RD_REGULATOR_SECTION 0x1000 637*e65e175bSOded Gabbay #define mmTPC7_WR_REGULATOR_BASE 0x7FFCFC5000ull 638*e65e175bSOded Gabbay #define TPC7_WR_REGULATOR_MAX_OFFSET 0x74 639*e65e175bSOded Gabbay #define TPC7_WR_REGULATOR_SECTION 0x1000 640*e65e175bSOded Gabbay #define mmTPC7_CFG_BASE 0x7FFCFC6000ull 641*e65e175bSOded Gabbay #define TPC7_CFG_MAX_OFFSET 0xE30 642*e65e175bSOded Gabbay #define TPC7_CFG_SECTION 0x2000 643*e65e175bSOded Gabbay #define mmTPC7_QM_BASE 0x7FFCFC8000ull 644*e65e175bSOded Gabbay #define TPC7_QM_MAX_OFFSET 0x310 645*e65e175bSOded Gabbay #define TPC7_QM_SECTION 0x1000 646*e65e175bSOded Gabbay #define mmTPC7_CMDQ_BASE 0x7FFCFC9000ull 647*e65e175bSOded Gabbay #define TPC7_CMDQ_MAX_OFFSET 0x310 648*e65e175bSOded Gabbay #define TPC7_CMDQ_SECTION 0x1037000 649*e65e175bSOded Gabbay #define mmMME_TOP_TABLE_BASE 0x7FFE000000ull 650*e65e175bSOded Gabbay #define MME_TOP_TABLE_MAX_OFFSET 0x1000 651*e65e175bSOded Gabbay #define MME_TOP_TABLE_SECTION 0x1000 652*e65e175bSOded Gabbay #define mmMME0_RTR_FUNNEL_BASE 0x7FFE001000ull 653*e65e175bSOded Gabbay #define MME0_RTR_FUNNEL_MAX_OFFSET 0x1000 654*e65e175bSOded Gabbay #define MME0_RTR_FUNNEL_SECTION 0x40000 655*e65e175bSOded Gabbay #define mmMME1_RTR_FUNNEL_BASE 0x7FFE041000ull 656*e65e175bSOded Gabbay #define MME1_RTR_FUNNEL_MAX_OFFSET 0x1000 657*e65e175bSOded Gabbay #define MME1_RTR_FUNNEL_SECTION 0x1000 658*e65e175bSOded Gabbay #define mmMME1_SBA_STM_BASE 0x7FFE042000ull 659*e65e175bSOded Gabbay #define MME1_SBA_STM_MAX_OFFSET 0x1000 660*e65e175bSOded Gabbay #define MME1_SBA_STM_SECTION 0x1000 661*e65e175bSOded Gabbay #define mmMME1_SBA_CTI_BASE 0x7FFE043000ull 662*e65e175bSOded Gabbay #define MME1_SBA_CTI_MAX_OFFSET 0x1000 663*e65e175bSOded Gabbay #define MME1_SBA_CTI_SECTION 0x1000 664*e65e175bSOded Gabbay #define mmMME1_SBA_ETF_BASE 0x7FFE044000ull 665*e65e175bSOded Gabbay #define MME1_SBA_ETF_MAX_OFFSET 0x1000 666*e65e175bSOded Gabbay #define MME1_SBA_ETF_SECTION 0x1000 667*e65e175bSOded Gabbay #define mmMME1_SBA_SPMU_BASE 0x7FFE045000ull 668*e65e175bSOded Gabbay #define MME1_SBA_SPMU_MAX_OFFSET 0x1000 669*e65e175bSOded Gabbay #define MME1_SBA_SPMU_SECTION 0x1000 670*e65e175bSOded Gabbay #define mmMME1_SBA_CTI0_BASE 0x7FFE046000ull 671*e65e175bSOded Gabbay #define MME1_SBA_CTI0_MAX_OFFSET 0x1000 672*e65e175bSOded Gabbay #define MME1_SBA_CTI0_SECTION 0x1000 673*e65e175bSOded Gabbay #define mmMME1_SBA_CTI1_BASE 0x7FFE047000ull 674*e65e175bSOded Gabbay #define MME1_SBA_CTI1_MAX_OFFSET 0x1000 675*e65e175bSOded Gabbay #define MME1_SBA_CTI1_SECTION 0x1000 676*e65e175bSOded Gabbay #define mmMME1_SBA_BMON0_BASE 0x7FFE048000ull 677*e65e175bSOded Gabbay #define MME1_SBA_BMON0_MAX_OFFSET 0x1000 678*e65e175bSOded Gabbay #define MME1_SBA_BMON0_SECTION 0x1000 679*e65e175bSOded Gabbay #define mmMME1_SBA_BMON1_BASE 0x7FFE049000ull 680*e65e175bSOded Gabbay #define MME1_SBA_BMON1_MAX_OFFSET 0x1000 681*e65e175bSOded Gabbay #define MME1_SBA_BMON1_SECTION 0x38000 682*e65e175bSOded Gabbay #define mmMME2_RTR_FUNNEL_BASE 0x7FFE081000ull 683*e65e175bSOded Gabbay #define MME2_RTR_FUNNEL_MAX_OFFSET 0x1000 684*e65e175bSOded Gabbay #define MME2_RTR_FUNNEL_SECTION 0x40000 685*e65e175bSOded Gabbay #define mmMME3_RTR_FUNNEL_BASE 0x7FFE0C1000ull 686*e65e175bSOded Gabbay #define MME3_RTR_FUNNEL_MAX_OFFSET 0x1000 687*e65e175bSOded Gabbay #define MME3_RTR_FUNNEL_SECTION 0x1000 688*e65e175bSOded Gabbay #define mmMME3_SBB_STM_BASE 0x7FFE0C2000ull 689*e65e175bSOded Gabbay #define MME3_SBB_STM_MAX_OFFSET 0x1000 690*e65e175bSOded Gabbay #define MME3_SBB_STM_SECTION 0x1000 691*e65e175bSOded Gabbay #define mmMME3_SBB_CTI_BASE 0x7FFE0C3000ull 692*e65e175bSOded Gabbay #define MME3_SBB_CTI_MAX_OFFSET 0x1000 693*e65e175bSOded Gabbay #define MME3_SBB_CTI_SECTION 0x1000 694*e65e175bSOded Gabbay #define mmMME3_SBB_ETF_BASE 0x7FFE0C4000ull 695*e65e175bSOded Gabbay #define MME3_SBB_ETF_MAX_OFFSET 0x1000 696*e65e175bSOded Gabbay #define MME3_SBB_ETF_SECTION 0x1000 697*e65e175bSOded Gabbay #define mmMME3_SBB_SPMU_BASE 0x7FFE0C5000ull 698*e65e175bSOded Gabbay #define MME3_SBB_SPMU_MAX_OFFSET 0x1000 699*e65e175bSOded Gabbay #define MME3_SBB_SPMU_SECTION 0x1000 700*e65e175bSOded Gabbay #define mmMME3_SBB_CTI0_BASE 0x7FFE0C6000ull 701*e65e175bSOded Gabbay #define MME3_SBB_CTI0_MAX_OFFSET 0x1000 702*e65e175bSOded Gabbay #define MME3_SBB_CTI0_SECTION 0x1000 703*e65e175bSOded Gabbay #define mmMME3_SBB_CTI1_BASE 0x7FFE0C7000ull 704*e65e175bSOded Gabbay #define MME3_SBB_CTI1_MAX_OFFSET 0x1000 705*e65e175bSOded Gabbay #define MME3_SBB_CTI1_SECTION 0x1000 706*e65e175bSOded Gabbay #define mmMME3_SBB_BMON0_BASE 0x7FFE0C8000ull 707*e65e175bSOded Gabbay #define MME3_SBB_BMON0_MAX_OFFSET 0x1000 708*e65e175bSOded Gabbay #define MME3_SBB_BMON0_SECTION 0x1000 709*e65e175bSOded Gabbay #define mmMME3_SBB_BMON1_BASE 0x7FFE0C9000ull 710*e65e175bSOded Gabbay #define MME3_SBB_BMON1_MAX_OFFSET 0x1000 711*e65e175bSOded Gabbay #define MME3_SBB_BMON1_SECTION 0x38000 712*e65e175bSOded Gabbay #define mmMME4_RTR_FUNNEL_BASE 0x7FFE101000ull 713*e65e175bSOded Gabbay #define MME4_RTR_FUNNEL_MAX_OFFSET 0x1000 714*e65e175bSOded Gabbay #define MME4_RTR_FUNNEL_SECTION 0x1000 715*e65e175bSOded Gabbay #define mmMME4_WACS_STM_BASE 0x7FFE102000ull 716*e65e175bSOded Gabbay #define MME4_WACS_STM_MAX_OFFSET 0x1000 717*e65e175bSOded Gabbay #define MME4_WACS_STM_SECTION 0x1000 718*e65e175bSOded Gabbay #define mmMME4_WACS_CTI_BASE 0x7FFE103000ull 719*e65e175bSOded Gabbay #define MME4_WACS_CTI_MAX_OFFSET 0x1000 720*e65e175bSOded Gabbay #define MME4_WACS_CTI_SECTION 0x1000 721*e65e175bSOded Gabbay #define mmMME4_WACS_ETF_BASE 0x7FFE104000ull 722*e65e175bSOded Gabbay #define MME4_WACS_ETF_MAX_OFFSET 0x1000 723*e65e175bSOded Gabbay #define MME4_WACS_ETF_SECTION 0x1000 724*e65e175bSOded Gabbay #define mmMME4_WACS_SPMU_BASE 0x7FFE105000ull 725*e65e175bSOded Gabbay #define MME4_WACS_SPMU_MAX_OFFSET 0x1000 726*e65e175bSOded Gabbay #define MME4_WACS_SPMU_SECTION 0x1000 727*e65e175bSOded Gabbay #define mmMME4_WACS_CTI0_BASE 0x7FFE106000ull 728*e65e175bSOded Gabbay #define MME4_WACS_CTI0_MAX_OFFSET 0x1000 729*e65e175bSOded Gabbay #define MME4_WACS_CTI0_SECTION 0x1000 730*e65e175bSOded Gabbay #define mmMME4_WACS_CTI1_BASE 0x7FFE107000ull 731*e65e175bSOded Gabbay #define MME4_WACS_CTI1_MAX_OFFSET 0x1000 732*e65e175bSOded Gabbay #define MME4_WACS_CTI1_SECTION 0x1000 733*e65e175bSOded Gabbay #define mmMME4_WACS_BMON0_BASE 0x7FFE108000ull 734*e65e175bSOded Gabbay #define MME4_WACS_BMON0_MAX_OFFSET 0x1000 735*e65e175bSOded Gabbay #define MME4_WACS_BMON0_SECTION 0x1000 736*e65e175bSOded Gabbay #define mmMME4_WACS_BMON1_BASE 0x7FFE109000ull 737*e65e175bSOded Gabbay #define MME4_WACS_BMON1_MAX_OFFSET 0x1000 738*e65e175bSOded Gabbay #define MME4_WACS_BMON1_SECTION 0x1000 739*e65e175bSOded Gabbay #define mmMME4_WACS_BMON2_BASE 0x7FFE10A000ull 740*e65e175bSOded Gabbay #define MME4_WACS_BMON2_MAX_OFFSET 0x1000 741*e65e175bSOded Gabbay #define MME4_WACS_BMON2_SECTION 0x1000 742*e65e175bSOded Gabbay #define mmMME4_WACS_BMON3_BASE 0x7FFE10B000ull 743*e65e175bSOded Gabbay #define MME4_WACS_BMON3_MAX_OFFSET 0x1000 744*e65e175bSOded Gabbay #define MME4_WACS_BMON3_SECTION 0x1000 745*e65e175bSOded Gabbay #define mmMME4_WACS_BMON4_BASE 0x7FFE10C000ull 746*e65e175bSOded Gabbay #define MME4_WACS_BMON4_MAX_OFFSET 0x1000 747*e65e175bSOded Gabbay #define MME4_WACS_BMON4_SECTION 0x1000 748*e65e175bSOded Gabbay #define mmMME4_WACS_BMON5_BASE 0x7FFE10D000ull 749*e65e175bSOded Gabbay #define MME4_WACS_BMON5_MAX_OFFSET 0x1000 750*e65e175bSOded Gabbay #define MME4_WACS_BMON5_SECTION 0x1000 751*e65e175bSOded Gabbay #define mmMME4_WACS_BMON6_BASE 0x7FFE10E000ull 752*e65e175bSOded Gabbay #define MME4_WACS_BMON6_MAX_OFFSET 0x1000 753*e65e175bSOded Gabbay #define MME4_WACS_BMON6_SECTION 0x4000 754*e65e175bSOded Gabbay #define mmMME4_WACS2_STM_BASE 0x7FFE112000ull 755*e65e175bSOded Gabbay #define MME4_WACS2_STM_MAX_OFFSET 0x1000 756*e65e175bSOded Gabbay #define MME4_WACS2_STM_SECTION 0x1000 757*e65e175bSOded Gabbay #define mmMME4_WACS2_CTI_BASE 0x7FFE113000ull 758*e65e175bSOded Gabbay #define MME4_WACS2_CTI_MAX_OFFSET 0x1000 759*e65e175bSOded Gabbay #define MME4_WACS2_CTI_SECTION 0x1000 760*e65e175bSOded Gabbay #define mmMME4_WACS2_ETF_BASE 0x7FFE114000ull 761*e65e175bSOded Gabbay #define MME4_WACS2_ETF_MAX_OFFSET 0x1000 762*e65e175bSOded Gabbay #define MME4_WACS2_ETF_SECTION 0x1000 763*e65e175bSOded Gabbay #define mmMME4_WACS2_SPMU_BASE 0x7FFE115000ull 764*e65e175bSOded Gabbay #define MME4_WACS2_SPMU_MAX_OFFSET 0x1000 765*e65e175bSOded Gabbay #define MME4_WACS2_SPMU_SECTION 0x1000 766*e65e175bSOded Gabbay #define mmMME4_WACS2_CTI0_BASE 0x7FFE116000ull 767*e65e175bSOded Gabbay #define MME4_WACS2_CTI0_MAX_OFFSET 0x1000 768*e65e175bSOded Gabbay #define MME4_WACS2_CTI0_SECTION 0x1000 769*e65e175bSOded Gabbay #define mmMME4_WACS2_CTI1_BASE 0x7FFE117000ull 770*e65e175bSOded Gabbay #define MME4_WACS2_CTI1_MAX_OFFSET 0x1000 771*e65e175bSOded Gabbay #define MME4_WACS2_CTI1_SECTION 0x1000 772*e65e175bSOded Gabbay #define mmMME4_WACS2_BMON0_BASE 0x7FFE118000ull 773*e65e175bSOded Gabbay #define MME4_WACS2_BMON0_MAX_OFFSET 0x1000 774*e65e175bSOded Gabbay #define MME4_WACS2_BMON0_SECTION 0x1000 775*e65e175bSOded Gabbay #define mmMME4_WACS2_BMON1_BASE 0x7FFE119000ull 776*e65e175bSOded Gabbay #define MME4_WACS2_BMON1_MAX_OFFSET 0x1000 777*e65e175bSOded Gabbay #define MME4_WACS2_BMON1_SECTION 0x1000 778*e65e175bSOded Gabbay #define mmMME4_WACS2_BMON2_BASE 0x7FFE11A000ull 779*e65e175bSOded Gabbay #define MME4_WACS2_BMON2_MAX_OFFSET 0x1000 780*e65e175bSOded Gabbay #define MME4_WACS2_BMON2_SECTION 0x27000 781*e65e175bSOded Gabbay #define mmMME5_RTR_FUNNEL_BASE 0x7FFE141000ull 782*e65e175bSOded Gabbay #define MME5_RTR_FUNNEL_MAX_OFFSET 0x1000 783*e65e175bSOded Gabbay #define MME5_RTR_FUNNEL_SECTION 0x2BF000 784*e65e175bSOded Gabbay #define mmDMA_ROM_TABLE_BASE 0x7FFE400000ull 785*e65e175bSOded Gabbay #define DMA_ROM_TABLE_MAX_OFFSET 0x1000 786*e65e175bSOded Gabbay #define DMA_ROM_TABLE_SECTION 0x1000 787*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_STM_BASE 0x7FFE401000ull 788*e65e175bSOded Gabbay #define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 789*e65e175bSOded Gabbay #define DMA_CH_0_CS_STM_SECTION 0x1000 790*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_CTI_BASE 0x7FFE402000ull 791*e65e175bSOded Gabbay #define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 792*e65e175bSOded Gabbay #define DMA_CH_0_CS_CTI_SECTION 0x1000 793*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_ETF_BASE 0x7FFE403000ull 794*e65e175bSOded Gabbay #define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 795*e65e175bSOded Gabbay #define DMA_CH_0_CS_ETF_SECTION 0x1000 796*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE404000ull 797*e65e175bSOded Gabbay #define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 798*e65e175bSOded Gabbay #define DMA_CH_0_CS_SPMU_SECTION 0x1000 799*e65e175bSOded Gabbay #define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE405000ull 800*e65e175bSOded Gabbay #define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 801*e65e175bSOded Gabbay #define DMA_CH_0_BMON_CTI_SECTION 0x1000 802*e65e175bSOded Gabbay #define mmDMA_CH_0_USER_CTI_BASE 0x7FFE406000ull 803*e65e175bSOded Gabbay #define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 804*e65e175bSOded Gabbay #define DMA_CH_0_USER_CTI_SECTION 0x1000 805*e65e175bSOded Gabbay #define mmDMA_CH_0_BMON_0_BASE 0x7FFE407000ull 806*e65e175bSOded Gabbay #define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 807*e65e175bSOded Gabbay #define DMA_CH_0_BMON_0_SECTION 0x1000 808*e65e175bSOded Gabbay #define mmDMA_CH_0_BMON_1_BASE 0x7FFE408000ull 809*e65e175bSOded Gabbay #define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 810*e65e175bSOded Gabbay #define DMA_CH_0_BMON_1_SECTION 0x9000 811*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_STM_BASE 0x7FFE411000ull 812*e65e175bSOded Gabbay #define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 813*e65e175bSOded Gabbay #define DMA_CH_1_CS_STM_SECTION 0x1000 814*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_CTI_BASE 0x7FFE412000ull 815*e65e175bSOded Gabbay #define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 816*e65e175bSOded Gabbay #define DMA_CH_1_CS_CTI_SECTION 0x1000 817*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_ETF_BASE 0x7FFE413000ull 818*e65e175bSOded Gabbay #define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 819*e65e175bSOded Gabbay #define DMA_CH_1_CS_ETF_SECTION 0x1000 820*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE414000ull 821*e65e175bSOded Gabbay #define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 822*e65e175bSOded Gabbay #define DMA_CH_1_CS_SPMU_SECTION 0x1000 823*e65e175bSOded Gabbay #define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE415000ull 824*e65e175bSOded Gabbay #define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 825*e65e175bSOded Gabbay #define DMA_CH_1_BMON_CTI_SECTION 0x1000 826*e65e175bSOded Gabbay #define mmDMA_CH_1_USER_CTI_BASE 0x7FFE416000ull 827*e65e175bSOded Gabbay #define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 828*e65e175bSOded Gabbay #define DMA_CH_1_USER_CTI_SECTION 0x1000 829*e65e175bSOded Gabbay #define mmDMA_CH_1_BMON_0_BASE 0x7FFE417000ull 830*e65e175bSOded Gabbay #define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 831*e65e175bSOded Gabbay #define DMA_CH_1_BMON_0_SECTION 0x1000 832*e65e175bSOded Gabbay #define mmDMA_CH_1_BMON_1_BASE 0x7FFE418000ull 833*e65e175bSOded Gabbay #define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 834*e65e175bSOded Gabbay #define DMA_CH_1_BMON_1_SECTION 0x9000 835*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_STM_BASE 0x7FFE421000ull 836*e65e175bSOded Gabbay #define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 837*e65e175bSOded Gabbay #define DMA_CH_2_CS_STM_SECTION 0x1000 838*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_CTI_BASE 0x7FFE422000ull 839*e65e175bSOded Gabbay #define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 840*e65e175bSOded Gabbay #define DMA_CH_2_CS_CTI_SECTION 0x1000 841*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_ETF_BASE 0x7FFE423000ull 842*e65e175bSOded Gabbay #define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 843*e65e175bSOded Gabbay #define DMA_CH_2_CS_ETF_SECTION 0x1000 844*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE424000ull 845*e65e175bSOded Gabbay #define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 846*e65e175bSOded Gabbay #define DMA_CH_2_CS_SPMU_SECTION 0x1000 847*e65e175bSOded Gabbay #define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE425000ull 848*e65e175bSOded Gabbay #define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 849*e65e175bSOded Gabbay #define DMA_CH_2_BMON_CTI_SECTION 0x1000 850*e65e175bSOded Gabbay #define mmDMA_CH_2_USER_CTI_BASE 0x7FFE426000ull 851*e65e175bSOded Gabbay #define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 852*e65e175bSOded Gabbay #define DMA_CH_2_USER_CTI_SECTION 0x1000 853*e65e175bSOded Gabbay #define mmDMA_CH_2_BMON_0_BASE 0x7FFE427000ull 854*e65e175bSOded Gabbay #define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 855*e65e175bSOded Gabbay #define DMA_CH_2_BMON_0_SECTION 0x1000 856*e65e175bSOded Gabbay #define mmDMA_CH_2_BMON_1_BASE 0x7FFE428000ull 857*e65e175bSOded Gabbay #define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 858*e65e175bSOded Gabbay #define DMA_CH_2_BMON_1_SECTION 0x9000 859*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_STM_BASE 0x7FFE431000ull 860*e65e175bSOded Gabbay #define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 861*e65e175bSOded Gabbay #define DMA_CH_3_CS_STM_SECTION 0x1000 862*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_CTI_BASE 0x7FFE432000ull 863*e65e175bSOded Gabbay #define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 864*e65e175bSOded Gabbay #define DMA_CH_3_CS_CTI_SECTION 0x1000 865*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_ETF_BASE 0x7FFE433000ull 866*e65e175bSOded Gabbay #define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 867*e65e175bSOded Gabbay #define DMA_CH_3_CS_ETF_SECTION 0x1000 868*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE434000ull 869*e65e175bSOded Gabbay #define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 870*e65e175bSOded Gabbay #define DMA_CH_3_CS_SPMU_SECTION 0x1000 871*e65e175bSOded Gabbay #define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE435000ull 872*e65e175bSOded Gabbay #define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 873*e65e175bSOded Gabbay #define DMA_CH_3_BMON_CTI_SECTION 0x1000 874*e65e175bSOded Gabbay #define mmDMA_CH_3_USER_CTI_BASE 0x7FFE436000ull 875*e65e175bSOded Gabbay #define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 876*e65e175bSOded Gabbay #define DMA_CH_3_USER_CTI_SECTION 0x1000 877*e65e175bSOded Gabbay #define mmDMA_CH_3_BMON_0_BASE 0x7FFE437000ull 878*e65e175bSOded Gabbay #define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 879*e65e175bSOded Gabbay #define DMA_CH_3_BMON_0_SECTION 0x1000 880*e65e175bSOded Gabbay #define mmDMA_CH_3_BMON_1_BASE 0x7FFE438000ull 881*e65e175bSOded Gabbay #define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 882*e65e175bSOded Gabbay #define DMA_CH_3_BMON_1_SECTION 0x9000 883*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_STM_BASE 0x7FFE441000ull 884*e65e175bSOded Gabbay #define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 885*e65e175bSOded Gabbay #define DMA_CH_4_CS_STM_SECTION 0x1000 886*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_CTI_BASE 0x7FFE442000ull 887*e65e175bSOded Gabbay #define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 888*e65e175bSOded Gabbay #define DMA_CH_4_CS_CTI_SECTION 0x1000 889*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_ETF_BASE 0x7FFE443000ull 890*e65e175bSOded Gabbay #define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 891*e65e175bSOded Gabbay #define DMA_CH_4_CS_ETF_SECTION 0x1000 892*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE444000ull 893*e65e175bSOded Gabbay #define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 894*e65e175bSOded Gabbay #define DMA_CH_4_CS_SPMU_SECTION 0x1000 895*e65e175bSOded Gabbay #define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE445000ull 896*e65e175bSOded Gabbay #define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 897*e65e175bSOded Gabbay #define DMA_CH_4_BMON_CTI_SECTION 0x1000 898*e65e175bSOded Gabbay #define mmDMA_CH_4_USER_CTI_BASE 0x7FFE446000ull 899*e65e175bSOded Gabbay #define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 900*e65e175bSOded Gabbay #define DMA_CH_4_USER_CTI_SECTION 0x1000 901*e65e175bSOded Gabbay #define mmDMA_CH_4_BMON_0_BASE 0x7FFE447000ull 902*e65e175bSOded Gabbay #define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 903*e65e175bSOded Gabbay #define DMA_CH_4_BMON_0_SECTION 0x1000 904*e65e175bSOded Gabbay #define mmDMA_CH_4_BMON_1_BASE 0x7FFE448000ull 905*e65e175bSOded Gabbay #define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 906*e65e175bSOded Gabbay #define DMA_CH_4_BMON_1_SECTION 0x8000 907*e65e175bSOded Gabbay #define mmDMA_CH_FUNNEL_6_1_BASE 0x7FFE450000ull 908*e65e175bSOded Gabbay #define DMA_CH_FUNNEL_6_1_MAX_OFFSET 0x1000 909*e65e175bSOded Gabbay #define DMA_CH_FUNNEL_6_1_SECTION 0x11000 910*e65e175bSOded Gabbay #define mmDMA_MACRO_CS_STM_BASE 0x7FFE461000ull 911*e65e175bSOded Gabbay #define DMA_MACRO_CS_STM_MAX_OFFSET 0x1000 912*e65e175bSOded Gabbay #define DMA_MACRO_CS_STM_SECTION 0x1000 913*e65e175bSOded Gabbay #define mmDMA_MACRO_CS_CTI_BASE 0x7FFE462000ull 914*e65e175bSOded Gabbay #define DMA_MACRO_CS_CTI_MAX_OFFSET 0x1000 915*e65e175bSOded Gabbay #define DMA_MACRO_CS_CTI_SECTION 0x1000 916*e65e175bSOded Gabbay #define mmDMA_MACRO_CS_ETF_BASE 0x7FFE463000ull 917*e65e175bSOded Gabbay #define DMA_MACRO_CS_ETF_MAX_OFFSET 0x1000 918*e65e175bSOded Gabbay #define DMA_MACRO_CS_ETF_SECTION 0x1000 919*e65e175bSOded Gabbay #define mmDMA_MACRO_CS_SPMU_BASE 0x7FFE464000ull 920*e65e175bSOded Gabbay #define DMA_MACRO_CS_SPMU_MAX_OFFSET 0x1000 921*e65e175bSOded Gabbay #define DMA_MACRO_CS_SPMU_SECTION 0x1000 922*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_CTI_BASE 0x7FFE465000ull 923*e65e175bSOded Gabbay #define DMA_MACRO_BMON_CTI_MAX_OFFSET 0x1000 924*e65e175bSOded Gabbay #define DMA_MACRO_BMON_CTI_SECTION 0x1000 925*e65e175bSOded Gabbay #define mmDMA_MACRO_USER_CTI_BASE 0x7FFE466000ull 926*e65e175bSOded Gabbay #define DMA_MACRO_USER_CTI_MAX_OFFSET 0x1000 927*e65e175bSOded Gabbay #define DMA_MACRO_USER_CTI_SECTION 0x1000 928*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_0_BASE 0x7FFE467000ull 929*e65e175bSOded Gabbay #define DMA_MACRO_BMON_0_MAX_OFFSET 0x1000 930*e65e175bSOded Gabbay #define DMA_MACRO_BMON_0_SECTION 0x1000 931*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_1_BASE 0x7FFE468000ull 932*e65e175bSOded Gabbay #define DMA_MACRO_BMON_1_MAX_OFFSET 0x1000 933*e65e175bSOded Gabbay #define DMA_MACRO_BMON_1_SECTION 0x1000 934*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_2_BASE 0x7FFE469000ull 935*e65e175bSOded Gabbay #define DMA_MACRO_BMON_2_MAX_OFFSET 0x1000 936*e65e175bSOded Gabbay #define DMA_MACRO_BMON_2_SECTION 0x1000 937*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_3_BASE 0x7FFE46A000ull 938*e65e175bSOded Gabbay #define DMA_MACRO_BMON_3_MAX_OFFSET 0x1000 939*e65e175bSOded Gabbay #define DMA_MACRO_BMON_3_SECTION 0x1000 940*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_4_BASE 0x7FFE46B000ull 941*e65e175bSOded Gabbay #define DMA_MACRO_BMON_4_MAX_OFFSET 0x1000 942*e65e175bSOded Gabbay #define DMA_MACRO_BMON_4_SECTION 0x1000 943*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_5_BASE 0x7FFE46C000ull 944*e65e175bSOded Gabbay #define DMA_MACRO_BMON_5_MAX_OFFSET 0x1000 945*e65e175bSOded Gabbay #define DMA_MACRO_BMON_5_SECTION 0x1000 946*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_6_BASE 0x7FFE46D000ull 947*e65e175bSOded Gabbay #define DMA_MACRO_BMON_6_MAX_OFFSET 0x1000 948*e65e175bSOded Gabbay #define DMA_MACRO_BMON_6_SECTION 0x1000 949*e65e175bSOded Gabbay #define mmDMA_MACRO_BMON_7_BASE 0x7FFE46E000ull 950*e65e175bSOded Gabbay #define DMA_MACRO_BMON_7_MAX_OFFSET 0x1000 951*e65e175bSOded Gabbay #define DMA_MACRO_BMON_7_SECTION 0x2000 952*e65e175bSOded Gabbay #define mmDMA_MACRO_FUNNEL_3_1_BASE 0x7FFE470000ull 953*e65e175bSOded Gabbay #define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET 0x1000 954*e65e175bSOded Gabbay #define DMA_MACRO_FUNNEL_3_1_SECTION 0x10000 955*e65e175bSOded Gabbay #define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull 956*e65e175bSOded Gabbay #define CPU_ROM_TABLE_MAX_OFFSET 0x1000 957*e65e175bSOded Gabbay #define CPU_ROM_TABLE_SECTION 0x1000 958*e65e175bSOded Gabbay #define mmCPU_ETF_0_BASE 0x7FFE481000ull 959*e65e175bSOded Gabbay #define CPU_ETF_0_MAX_OFFSET 0x1000 960*e65e175bSOded Gabbay #define CPU_ETF_0_SECTION 0x1000 961*e65e175bSOded Gabbay #define mmCPU_ETF_1_BASE 0x7FFE482000ull 962*e65e175bSOded Gabbay #define CPU_ETF_1_MAX_OFFSET 0x1000 963*e65e175bSOded Gabbay #define CPU_ETF_1_SECTION 0x2000 964*e65e175bSOded Gabbay #define mmCPU_CTI_BASE 0x7FFE484000ull 965*e65e175bSOded Gabbay #define CPU_CTI_MAX_OFFSET 0x1000 966*e65e175bSOded Gabbay #define CPU_CTI_SECTION 0x1000 967*e65e175bSOded Gabbay #define mmCPU_FUNNEL_BASE 0x7FFE485000ull 968*e65e175bSOded Gabbay #define CPU_FUNNEL_MAX_OFFSET 0x1000 969*e65e175bSOded Gabbay #define CPU_FUNNEL_SECTION 0x1000 970*e65e175bSOded Gabbay #define mmCPU_STM_BASE 0x7FFE486000ull 971*e65e175bSOded Gabbay #define CPU_STM_MAX_OFFSET 0x1000 972*e65e175bSOded Gabbay #define CPU_STM_SECTION 0x1000 973*e65e175bSOded Gabbay #define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull 974*e65e175bSOded Gabbay #define CPU_CTI_TRACE_MAX_OFFSET 0x1000 975*e65e175bSOded Gabbay #define CPU_CTI_TRACE_SECTION 0x1000 976*e65e175bSOded Gabbay #define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull 977*e65e175bSOded Gabbay #define CPU_ETF_TRACE_MAX_OFFSET 0x1000 978*e65e175bSOded Gabbay #define CPU_ETF_TRACE_SECTION 0x1000 979*e65e175bSOded Gabbay #define mmCPU_WR_BMON_BASE 0x7FFE489000ull 980*e65e175bSOded Gabbay #define CPU_WR_BMON_MAX_OFFSET 0x1000 981*e65e175bSOded Gabbay #define CPU_WR_BMON_SECTION 0x1000 982*e65e175bSOded Gabbay #define mmCPU_RD_BMON_BASE 0x7FFE48A000ull 983*e65e175bSOded Gabbay #define CPU_RD_BMON_MAX_OFFSET 0x1000 984*e65e175bSOded Gabbay #define CPU_RD_BMON_SECTION 0x37000 985*e65e175bSOded Gabbay #define mmMMU_CS_STM_BASE 0x7FFE4C1000ull 986*e65e175bSOded Gabbay #define MMU_CS_STM_MAX_OFFSET 0x1000 987*e65e175bSOded Gabbay #define MMU_CS_STM_SECTION 0x1000 988*e65e175bSOded Gabbay #define mmMMU_CS_CTI_BASE 0x7FFE4C2000ull 989*e65e175bSOded Gabbay #define MMU_CS_CTI_MAX_OFFSET 0x1000 990*e65e175bSOded Gabbay #define MMU_CS_CTI_SECTION 0x1000 991*e65e175bSOded Gabbay #define mmMMU_CS_ETF_BASE 0x7FFE4C3000ull 992*e65e175bSOded Gabbay #define MMU_CS_ETF_MAX_OFFSET 0x1000 993*e65e175bSOded Gabbay #define MMU_CS_ETF_SECTION 0x1000 994*e65e175bSOded Gabbay #define mmMMU_CS_SPMU_BASE 0x7FFE4C4000ull 995*e65e175bSOded Gabbay #define MMU_CS_SPMU_MAX_OFFSET 0x1000 996*e65e175bSOded Gabbay #define MMU_CS_SPMU_SECTION 0x1000 997*e65e175bSOded Gabbay #define mmMMU_BMON_CTI_BASE 0x7FFE4C5000ull 998*e65e175bSOded Gabbay #define MMU_BMON_CTI_MAX_OFFSET 0x1000 999*e65e175bSOded Gabbay #define MMU_BMON_CTI_SECTION 0x1000 1000*e65e175bSOded Gabbay #define mmMMU_USER_CTI_BASE 0x7FFE4C6000ull 1001*e65e175bSOded Gabbay #define MMU_USER_CTI_MAX_OFFSET 0x1000 1002*e65e175bSOded Gabbay #define MMU_USER_CTI_SECTION 0x1000 1003*e65e175bSOded Gabbay #define mmMMU_BMON_0_BASE 0x7FFE4C7000ull 1004*e65e175bSOded Gabbay #define MMU_BMON_0_MAX_OFFSET 0x1000 1005*e65e175bSOded Gabbay #define MMU_BMON_0_SECTION 0x1000 1006*e65e175bSOded Gabbay #define mmMMU_BMON_1_BASE 0x7FFE4C8000ull 1007*e65e175bSOded Gabbay #define MMU_BMON_1_MAX_OFFSET 0x1000 1008*e65e175bSOded Gabbay #define MMU_BMON_1_SECTION 0x338000 1009*e65e175bSOded Gabbay #define mmCA53_BASE 0x7FFE800000ull 1010*e65e175bSOded Gabbay #define CA53_MAX_OFFSET 0x1000 1011*e65e175bSOded Gabbay #define CA53_SECTION 0x400000 1012*e65e175bSOded Gabbay #define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull 1013*e65e175bSOded Gabbay #define PCI_ROM_TABLE_MAX_OFFSET 0x1000 1014*e65e175bSOded Gabbay #define PCI_ROM_TABLE_SECTION 0x1000 1015*e65e175bSOded Gabbay #define mmPCIE_STM_BASE 0x7FFEC01000ull 1016*e65e175bSOded Gabbay #define PCIE_STM_MAX_OFFSET 0x1000 1017*e65e175bSOded Gabbay #define PCIE_STM_SECTION 0x1000 1018*e65e175bSOded Gabbay #define mmPCIE_ETF_BASE 0x7FFEC02000ull 1019*e65e175bSOded Gabbay #define PCIE_ETF_MAX_OFFSET 0x1000 1020*e65e175bSOded Gabbay #define PCIE_ETF_SECTION 0x1000 1021*e65e175bSOded Gabbay #define mmPCIE_CTI_0_BASE 0x7FFEC03000ull 1022*e65e175bSOded Gabbay #define PCIE_CTI_0_MAX_OFFSET 0x1000 1023*e65e175bSOded Gabbay #define PCIE_CTI_0_SECTION 0x1000 1024*e65e175bSOded Gabbay #define mmPCIE_SPMU_BASE 0x7FFEC04000ull 1025*e65e175bSOded Gabbay #define PCIE_SPMU_MAX_OFFSET 0x1000 1026*e65e175bSOded Gabbay #define PCIE_SPMU_SECTION 0x1000 1027*e65e175bSOded Gabbay #define mmPCIE_CTI_1_BASE 0x7FFEC05000ull 1028*e65e175bSOded Gabbay #define PCIE_CTI_1_MAX_OFFSET 0x1000 1029*e65e175bSOded Gabbay #define PCIE_CTI_1_SECTION 0x1000 1030*e65e175bSOded Gabbay #define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull 1031*e65e175bSOded Gabbay #define PCIE_FUNNEL_MAX_OFFSET 0x1000 1032*e65e175bSOded Gabbay #define PCIE_FUNNEL_SECTION 0x1000 1033*e65e175bSOded Gabbay #define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull 1034*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 1035*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_WR_SECTION 0x1000 1036*e65e175bSOded Gabbay #define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull 1037*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 1038*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_RD_SECTION 0x1000 1039*e65e175bSOded Gabbay #define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull 1040*e65e175bSOded Gabbay #define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 1041*e65e175bSOded Gabbay #define PCIE_BMON_SLV_WR_SECTION 0x1000 1042*e65e175bSOded Gabbay #define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull 1043*e65e175bSOded Gabbay #define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 1044*e65e175bSOded Gabbay #define PCIE_BMON_SLV_RD_SECTION 0x36000 1045*e65e175bSOded Gabbay #define mmPSOC_CTI_BASE 0x7FFEC40000ull 1046*e65e175bSOded Gabbay #define PSOC_CTI_MAX_OFFSET 0x1000 1047*e65e175bSOded Gabbay #define PSOC_CTI_SECTION 0x1000 1048*e65e175bSOded Gabbay #define mmPSOC_STM_BASE 0x7FFEC41000ull 1049*e65e175bSOded Gabbay #define PSOC_STM_MAX_OFFSET 0x1000 1050*e65e175bSOded Gabbay #define PSOC_STM_SECTION 0x1000 1051*e65e175bSOded Gabbay #define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull 1052*e65e175bSOded Gabbay #define PSOC_FUNNEL_MAX_OFFSET 0x1000 1053*e65e175bSOded Gabbay #define PSOC_FUNNEL_SECTION 0x1000 1054*e65e175bSOded Gabbay #define mmPSOC_ETR_BASE 0x7FFEC43000ull 1055*e65e175bSOded Gabbay #define PSOC_ETR_MAX_OFFSET 0x1000 1056*e65e175bSOded Gabbay #define PSOC_ETR_SECTION 0x1000 1057*e65e175bSOded Gabbay #define mmPSOC_ETF_BASE 0x7FFEC44000ull 1058*e65e175bSOded Gabbay #define PSOC_ETF_MAX_OFFSET 0x1000 1059*e65e175bSOded Gabbay #define PSOC_ETF_SECTION 0x1000 1060*e65e175bSOded Gabbay #define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull 1061*e65e175bSOded Gabbay #define PSOC_TS_CTI_MAX_OFFSET 0x1000 1062*e65e175bSOded Gabbay #define PSOC_TS_CTI_SECTION 0xB000 1063*e65e175bSOded Gabbay #define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull 1064*e65e175bSOded Gabbay #define TOP_ROM_TABLE_MAX_OFFSET 0x1000 1065*e65e175bSOded Gabbay #define TOP_ROM_TABLE_SECTION 0x1F0000 1066*e65e175bSOded Gabbay #define mmTPC1_RTR_FUNNEL_BASE 0x7FFEE40000ull 1067*e65e175bSOded Gabbay #define TPC1_RTR_FUNNEL_MAX_OFFSET 0x1000 1068*e65e175bSOded Gabbay #define TPC1_RTR_FUNNEL_SECTION 0x40000 1069*e65e175bSOded Gabbay #define mmTPC2_RTR_FUNNEL_BASE 0x7FFEE80000ull 1070*e65e175bSOded Gabbay #define TPC2_RTR_FUNNEL_MAX_OFFSET 0x1000 1071*e65e175bSOded Gabbay #define TPC2_RTR_FUNNEL_SECTION 0x40000 1072*e65e175bSOded Gabbay #define mmTPC3_RTR_FUNNEL_BASE 0x7FFEEC0000ull 1073*e65e175bSOded Gabbay #define TPC3_RTR_FUNNEL_MAX_OFFSET 0x1000 1074*e65e175bSOded Gabbay #define TPC3_RTR_FUNNEL_SECTION 0x40000 1075*e65e175bSOded Gabbay #define mmTPC4_RTR_FUNNEL_BASE 0x7FFEF00000ull 1076*e65e175bSOded Gabbay #define TPC4_RTR_FUNNEL_MAX_OFFSET 0x1000 1077*e65e175bSOded Gabbay #define TPC4_RTR_FUNNEL_SECTION 0x40000 1078*e65e175bSOded Gabbay #define mmTPC5_RTR_FUNNEL_BASE 0x7FFEF40000ull 1079*e65e175bSOded Gabbay #define TPC5_RTR_FUNNEL_MAX_OFFSET 0x1000 1080*e65e175bSOded Gabbay #define TPC5_RTR_FUNNEL_SECTION 0x40000 1081*e65e175bSOded Gabbay #define mmTPC6_RTR_FUNNEL_BASE 0x7FFEF80000ull 1082*e65e175bSOded Gabbay #define TPC6_RTR_FUNNEL_MAX_OFFSET 0x1000 1083*e65e175bSOded Gabbay #define TPC6_RTR_FUNNEL_SECTION 0x81000 1084*e65e175bSOded Gabbay #define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull 1085*e65e175bSOded Gabbay #define TPC0_EML_SPMU_MAX_OFFSET 0x1000 1086*e65e175bSOded Gabbay #define TPC0_EML_SPMU_SECTION 0x1000 1087*e65e175bSOded Gabbay #define mmTPC0_EML_ETF_BASE 0x7FFF002000ull 1088*e65e175bSOded Gabbay #define TPC0_EML_ETF_MAX_OFFSET 0x1000 1089*e65e175bSOded Gabbay #define TPC0_EML_ETF_SECTION 0x1000 1090*e65e175bSOded Gabbay #define mmTPC0_EML_STM_BASE 0x7FFF003000ull 1091*e65e175bSOded Gabbay #define TPC0_EML_STM_MAX_OFFSET 0x1000 1092*e65e175bSOded Gabbay #define TPC0_EML_STM_SECTION 0x1000 1093*e65e175bSOded Gabbay #define mmTPC0_EML_ETM_R4_BASE 0x7FFF004000ull 1094*e65e175bSOded Gabbay #define TPC0_EML_ETM_R4_MAX_OFFSET 0x0 1095*e65e175bSOded Gabbay #define TPC0_EML_ETM_R4_SECTION 0x1000 1096*e65e175bSOded Gabbay #define mmTPC0_EML_CTI_BASE 0x7FFF005000ull 1097*e65e175bSOded Gabbay #define TPC0_EML_CTI_MAX_OFFSET 0x1000 1098*e65e175bSOded Gabbay #define TPC0_EML_CTI_SECTION 0x1000 1099*e65e175bSOded Gabbay #define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull 1100*e65e175bSOded Gabbay #define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 1101*e65e175bSOded Gabbay #define TPC0_EML_FUNNEL_SECTION 0x1000 1102*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull 1103*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 1104*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_0_SECTION 0x1000 1105*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull 1106*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 1107*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_1_SECTION 0x1000 1108*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull 1109*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 1110*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_2_SECTION 0x1000 1111*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull 1112*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 1113*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_3_SECTION 0x36000 1114*e65e175bSOded Gabbay #define mmTPC0_EML_CFG_BASE 0x7FFF040000ull 1115*e65e175bSOded Gabbay #define TPC0_EML_CFG_MAX_OFFSET 0x338 1116*e65e175bSOded Gabbay #define TPC0_EML_CFG_SECTION 0x1BF000 1117*e65e175bSOded Gabbay #define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull 1118*e65e175bSOded Gabbay #define TPC0_EML_CS_MAX_OFFSET 0x1000 1119*e65e175bSOded Gabbay #define TPC0_EML_CS_SECTION 0x2000 1120*e65e175bSOded Gabbay #define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull 1121*e65e175bSOded Gabbay #define TPC1_EML_SPMU_MAX_OFFSET 0x1000 1122*e65e175bSOded Gabbay #define TPC1_EML_SPMU_SECTION 0x1000 1123*e65e175bSOded Gabbay #define mmTPC1_EML_ETF_BASE 0x7FFF202000ull 1124*e65e175bSOded Gabbay #define TPC1_EML_ETF_MAX_OFFSET 0x1000 1125*e65e175bSOded Gabbay #define TPC1_EML_ETF_SECTION 0x1000 1126*e65e175bSOded Gabbay #define mmTPC1_EML_STM_BASE 0x7FFF203000ull 1127*e65e175bSOded Gabbay #define TPC1_EML_STM_MAX_OFFSET 0x1000 1128*e65e175bSOded Gabbay #define TPC1_EML_STM_SECTION 0x1000 1129*e65e175bSOded Gabbay #define mmTPC1_EML_ETM_R4_BASE 0x7FFF204000ull 1130*e65e175bSOded Gabbay #define TPC1_EML_ETM_R4_MAX_OFFSET 0x0 1131*e65e175bSOded Gabbay #define TPC1_EML_ETM_R4_SECTION 0x1000 1132*e65e175bSOded Gabbay #define mmTPC1_EML_CTI_BASE 0x7FFF205000ull 1133*e65e175bSOded Gabbay #define TPC1_EML_CTI_MAX_OFFSET 0x1000 1134*e65e175bSOded Gabbay #define TPC1_EML_CTI_SECTION 0x1000 1135*e65e175bSOded Gabbay #define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull 1136*e65e175bSOded Gabbay #define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 1137*e65e175bSOded Gabbay #define TPC1_EML_FUNNEL_SECTION 0x1000 1138*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull 1139*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 1140*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_0_SECTION 0x1000 1141*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull 1142*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 1143*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_1_SECTION 0x1000 1144*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull 1145*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 1146*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_2_SECTION 0x1000 1147*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull 1148*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 1149*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_3_SECTION 0x36000 1150*e65e175bSOded Gabbay #define mmTPC1_EML_CFG_BASE 0x7FFF240000ull 1151*e65e175bSOded Gabbay #define TPC1_EML_CFG_MAX_OFFSET 0x338 1152*e65e175bSOded Gabbay #define TPC1_EML_CFG_SECTION 0x1BF000 1153*e65e175bSOded Gabbay #define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull 1154*e65e175bSOded Gabbay #define TPC1_EML_CS_MAX_OFFSET 0x1000 1155*e65e175bSOded Gabbay #define TPC1_EML_CS_SECTION 0x2000 1156*e65e175bSOded Gabbay #define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull 1157*e65e175bSOded Gabbay #define TPC2_EML_SPMU_MAX_OFFSET 0x1000 1158*e65e175bSOded Gabbay #define TPC2_EML_SPMU_SECTION 0x1000 1159*e65e175bSOded Gabbay #define mmTPC2_EML_ETF_BASE 0x7FFF402000ull 1160*e65e175bSOded Gabbay #define TPC2_EML_ETF_MAX_OFFSET 0x1000 1161*e65e175bSOded Gabbay #define TPC2_EML_ETF_SECTION 0x1000 1162*e65e175bSOded Gabbay #define mmTPC2_EML_STM_BASE 0x7FFF403000ull 1163*e65e175bSOded Gabbay #define TPC2_EML_STM_MAX_OFFSET 0x1000 1164*e65e175bSOded Gabbay #define TPC2_EML_STM_SECTION 0x1000 1165*e65e175bSOded Gabbay #define mmTPC2_EML_ETM_R4_BASE 0x7FFF404000ull 1166*e65e175bSOded Gabbay #define TPC2_EML_ETM_R4_MAX_OFFSET 0x0 1167*e65e175bSOded Gabbay #define TPC2_EML_ETM_R4_SECTION 0x1000 1168*e65e175bSOded Gabbay #define mmTPC2_EML_CTI_BASE 0x7FFF405000ull 1169*e65e175bSOded Gabbay #define TPC2_EML_CTI_MAX_OFFSET 0x1000 1170*e65e175bSOded Gabbay #define TPC2_EML_CTI_SECTION 0x1000 1171*e65e175bSOded Gabbay #define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull 1172*e65e175bSOded Gabbay #define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 1173*e65e175bSOded Gabbay #define TPC2_EML_FUNNEL_SECTION 0x1000 1174*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull 1175*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 1176*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_0_SECTION 0x1000 1177*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull 1178*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 1179*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_1_SECTION 0x1000 1180*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull 1181*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 1182*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_2_SECTION 0x1000 1183*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull 1184*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 1185*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_3_SECTION 0x36000 1186*e65e175bSOded Gabbay #define mmTPC2_EML_CFG_BASE 0x7FFF440000ull 1187*e65e175bSOded Gabbay #define TPC2_EML_CFG_MAX_OFFSET 0x338 1188*e65e175bSOded Gabbay #define TPC2_EML_CFG_SECTION 0x1BF000 1189*e65e175bSOded Gabbay #define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull 1190*e65e175bSOded Gabbay #define TPC2_EML_CS_MAX_OFFSET 0x1000 1191*e65e175bSOded Gabbay #define TPC2_EML_CS_SECTION 0x2000 1192*e65e175bSOded Gabbay #define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull 1193*e65e175bSOded Gabbay #define TPC3_EML_SPMU_MAX_OFFSET 0x1000 1194*e65e175bSOded Gabbay #define TPC3_EML_SPMU_SECTION 0x1000 1195*e65e175bSOded Gabbay #define mmTPC3_EML_ETF_BASE 0x7FFF602000ull 1196*e65e175bSOded Gabbay #define TPC3_EML_ETF_MAX_OFFSET 0x1000 1197*e65e175bSOded Gabbay #define TPC3_EML_ETF_SECTION 0x1000 1198*e65e175bSOded Gabbay #define mmTPC3_EML_STM_BASE 0x7FFF603000ull 1199*e65e175bSOded Gabbay #define TPC3_EML_STM_MAX_OFFSET 0x1000 1200*e65e175bSOded Gabbay #define TPC3_EML_STM_SECTION 0x1000 1201*e65e175bSOded Gabbay #define mmTPC3_EML_ETM_R4_BASE 0x7FFF604000ull 1202*e65e175bSOded Gabbay #define TPC3_EML_ETM_R4_MAX_OFFSET 0x0 1203*e65e175bSOded Gabbay #define TPC3_EML_ETM_R4_SECTION 0x1000 1204*e65e175bSOded Gabbay #define mmTPC3_EML_CTI_BASE 0x7FFF605000ull 1205*e65e175bSOded Gabbay #define TPC3_EML_CTI_MAX_OFFSET 0x1000 1206*e65e175bSOded Gabbay #define TPC3_EML_CTI_SECTION 0x1000 1207*e65e175bSOded Gabbay #define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull 1208*e65e175bSOded Gabbay #define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 1209*e65e175bSOded Gabbay #define TPC3_EML_FUNNEL_SECTION 0x1000 1210*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull 1211*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 1212*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_0_SECTION 0x1000 1213*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull 1214*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 1215*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_1_SECTION 0x1000 1216*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull 1217*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 1218*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_2_SECTION 0x1000 1219*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull 1220*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 1221*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_3_SECTION 0x36000 1222*e65e175bSOded Gabbay #define mmTPC3_EML_CFG_BASE 0x7FFF640000ull 1223*e65e175bSOded Gabbay #define TPC3_EML_CFG_MAX_OFFSET 0x338 1224*e65e175bSOded Gabbay #define TPC3_EML_CFG_SECTION 0x1BF000 1225*e65e175bSOded Gabbay #define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull 1226*e65e175bSOded Gabbay #define TPC3_EML_CS_MAX_OFFSET 0x1000 1227*e65e175bSOded Gabbay #define TPC3_EML_CS_SECTION 0x2000 1228*e65e175bSOded Gabbay #define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull 1229*e65e175bSOded Gabbay #define TPC4_EML_SPMU_MAX_OFFSET 0x1000 1230*e65e175bSOded Gabbay #define TPC4_EML_SPMU_SECTION 0x1000 1231*e65e175bSOded Gabbay #define mmTPC4_EML_ETF_BASE 0x7FFF802000ull 1232*e65e175bSOded Gabbay #define TPC4_EML_ETF_MAX_OFFSET 0x1000 1233*e65e175bSOded Gabbay #define TPC4_EML_ETF_SECTION 0x1000 1234*e65e175bSOded Gabbay #define mmTPC4_EML_STM_BASE 0x7FFF803000ull 1235*e65e175bSOded Gabbay #define TPC4_EML_STM_MAX_OFFSET 0x1000 1236*e65e175bSOded Gabbay #define TPC4_EML_STM_SECTION 0x1000 1237*e65e175bSOded Gabbay #define mmTPC4_EML_ETM_R4_BASE 0x7FFF804000ull 1238*e65e175bSOded Gabbay #define TPC4_EML_ETM_R4_MAX_OFFSET 0x0 1239*e65e175bSOded Gabbay #define TPC4_EML_ETM_R4_SECTION 0x1000 1240*e65e175bSOded Gabbay #define mmTPC4_EML_CTI_BASE 0x7FFF805000ull 1241*e65e175bSOded Gabbay #define TPC4_EML_CTI_MAX_OFFSET 0x1000 1242*e65e175bSOded Gabbay #define TPC4_EML_CTI_SECTION 0x1000 1243*e65e175bSOded Gabbay #define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull 1244*e65e175bSOded Gabbay #define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 1245*e65e175bSOded Gabbay #define TPC4_EML_FUNNEL_SECTION 0x1000 1246*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull 1247*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 1248*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_0_SECTION 0x1000 1249*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull 1250*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 1251*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_1_SECTION 0x1000 1252*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull 1253*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 1254*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_2_SECTION 0x1000 1255*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull 1256*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 1257*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_3_SECTION 0x36000 1258*e65e175bSOded Gabbay #define mmTPC4_EML_CFG_BASE 0x7FFF840000ull 1259*e65e175bSOded Gabbay #define TPC4_EML_CFG_MAX_OFFSET 0x338 1260*e65e175bSOded Gabbay #define TPC4_EML_CFG_SECTION 0x1BF000 1261*e65e175bSOded Gabbay #define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull 1262*e65e175bSOded Gabbay #define TPC4_EML_CS_MAX_OFFSET 0x1000 1263*e65e175bSOded Gabbay #define TPC4_EML_CS_SECTION 0x2000 1264*e65e175bSOded Gabbay #define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull 1265*e65e175bSOded Gabbay #define TPC5_EML_SPMU_MAX_OFFSET 0x1000 1266*e65e175bSOded Gabbay #define TPC5_EML_SPMU_SECTION 0x1000 1267*e65e175bSOded Gabbay #define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull 1268*e65e175bSOded Gabbay #define TPC5_EML_ETF_MAX_OFFSET 0x1000 1269*e65e175bSOded Gabbay #define TPC5_EML_ETF_SECTION 0x1000 1270*e65e175bSOded Gabbay #define mmTPC5_EML_STM_BASE 0x7FFFA03000ull 1271*e65e175bSOded Gabbay #define TPC5_EML_STM_MAX_OFFSET 0x1000 1272*e65e175bSOded Gabbay #define TPC5_EML_STM_SECTION 0x1000 1273*e65e175bSOded Gabbay #define mmTPC5_EML_ETM_R4_BASE 0x7FFFA04000ull 1274*e65e175bSOded Gabbay #define TPC5_EML_ETM_R4_MAX_OFFSET 0x0 1275*e65e175bSOded Gabbay #define TPC5_EML_ETM_R4_SECTION 0x1000 1276*e65e175bSOded Gabbay #define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull 1277*e65e175bSOded Gabbay #define TPC5_EML_CTI_MAX_OFFSET 0x1000 1278*e65e175bSOded Gabbay #define TPC5_EML_CTI_SECTION 0x1000 1279*e65e175bSOded Gabbay #define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull 1280*e65e175bSOded Gabbay #define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 1281*e65e175bSOded Gabbay #define TPC5_EML_FUNNEL_SECTION 0x1000 1282*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull 1283*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 1284*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_0_SECTION 0x1000 1285*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull 1286*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 1287*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_1_SECTION 0x1000 1288*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull 1289*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 1290*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_2_SECTION 0x1000 1291*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull 1292*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 1293*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_3_SECTION 0x36000 1294*e65e175bSOded Gabbay #define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull 1295*e65e175bSOded Gabbay #define TPC5_EML_CFG_MAX_OFFSET 0x338 1296*e65e175bSOded Gabbay #define TPC5_EML_CFG_SECTION 0x1BF000 1297*e65e175bSOded Gabbay #define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull 1298*e65e175bSOded Gabbay #define TPC5_EML_CS_MAX_OFFSET 0x1000 1299*e65e175bSOded Gabbay #define TPC5_EML_CS_SECTION 0x2000 1300*e65e175bSOded Gabbay #define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull 1301*e65e175bSOded Gabbay #define TPC6_EML_SPMU_MAX_OFFSET 0x1000 1302*e65e175bSOded Gabbay #define TPC6_EML_SPMU_SECTION 0x1000 1303*e65e175bSOded Gabbay #define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull 1304*e65e175bSOded Gabbay #define TPC6_EML_ETF_MAX_OFFSET 0x1000 1305*e65e175bSOded Gabbay #define TPC6_EML_ETF_SECTION 0x1000 1306*e65e175bSOded Gabbay #define mmTPC6_EML_STM_BASE 0x7FFFC03000ull 1307*e65e175bSOded Gabbay #define TPC6_EML_STM_MAX_OFFSET 0x1000 1308*e65e175bSOded Gabbay #define TPC6_EML_STM_SECTION 0x1000 1309*e65e175bSOded Gabbay #define mmTPC6_EML_ETM_R4_BASE 0x7FFFC04000ull 1310*e65e175bSOded Gabbay #define TPC6_EML_ETM_R4_MAX_OFFSET 0x0 1311*e65e175bSOded Gabbay #define TPC6_EML_ETM_R4_SECTION 0x1000 1312*e65e175bSOded Gabbay #define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull 1313*e65e175bSOded Gabbay #define TPC6_EML_CTI_MAX_OFFSET 0x1000 1314*e65e175bSOded Gabbay #define TPC6_EML_CTI_SECTION 0x1000 1315*e65e175bSOded Gabbay #define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull 1316*e65e175bSOded Gabbay #define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 1317*e65e175bSOded Gabbay #define TPC6_EML_FUNNEL_SECTION 0x1000 1318*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull 1319*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 1320*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_0_SECTION 0x1000 1321*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull 1322*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 1323*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_1_SECTION 0x1000 1324*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull 1325*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 1326*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_2_SECTION 0x1000 1327*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull 1328*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 1329*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_3_SECTION 0x36000 1330*e65e175bSOded Gabbay #define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull 1331*e65e175bSOded Gabbay #define TPC6_EML_CFG_MAX_OFFSET 0x338 1332*e65e175bSOded Gabbay #define TPC6_EML_CFG_SECTION 0x1BF000 1333*e65e175bSOded Gabbay #define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull 1334*e65e175bSOded Gabbay #define TPC6_EML_CS_MAX_OFFSET 0x1000 1335*e65e175bSOded Gabbay #define TPC6_EML_CS_SECTION 0x2000 1336*e65e175bSOded Gabbay #define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull 1337*e65e175bSOded Gabbay #define TPC7_EML_SPMU_MAX_OFFSET 0x1000 1338*e65e175bSOded Gabbay #define TPC7_EML_SPMU_SECTION 0x1000 1339*e65e175bSOded Gabbay #define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull 1340*e65e175bSOded Gabbay #define TPC7_EML_ETF_MAX_OFFSET 0x1000 1341*e65e175bSOded Gabbay #define TPC7_EML_ETF_SECTION 0x1000 1342*e65e175bSOded Gabbay #define mmTPC7_EML_STM_BASE 0x7FFFE03000ull 1343*e65e175bSOded Gabbay #define TPC7_EML_STM_MAX_OFFSET 0x1000 1344*e65e175bSOded Gabbay #define TPC7_EML_STM_SECTION 0x1000 1345*e65e175bSOded Gabbay #define mmTPC7_EML_ETM_R4_BASE 0x7FFFE04000ull 1346*e65e175bSOded Gabbay #define TPC7_EML_ETM_R4_MAX_OFFSET 0x0 1347*e65e175bSOded Gabbay #define TPC7_EML_ETM_R4_SECTION 0x1000 1348*e65e175bSOded Gabbay #define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull 1349*e65e175bSOded Gabbay #define TPC7_EML_CTI_MAX_OFFSET 0x1000 1350*e65e175bSOded Gabbay #define TPC7_EML_CTI_SECTION 0x1000 1351*e65e175bSOded Gabbay #define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull 1352*e65e175bSOded Gabbay #define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 1353*e65e175bSOded Gabbay #define TPC7_EML_FUNNEL_SECTION 0x1000 1354*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull 1355*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 1356*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_0_SECTION 0x1000 1357*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull 1358*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 1359*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_1_SECTION 0x1000 1360*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull 1361*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 1362*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_2_SECTION 0x1000 1363*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull 1364*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 1365*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_3_SECTION 0x36000 1366*e65e175bSOded Gabbay #define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull 1367*e65e175bSOded Gabbay #define TPC7_EML_CFG_MAX_OFFSET 0x338 1368*e65e175bSOded Gabbay #define TPC7_EML_CFG_SECTION 0x1BF000 1369*e65e175bSOded Gabbay #define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull 1370*e65e175bSOded Gabbay #define TPC7_EML_CS_MAX_OFFSET 0x1000 1371*e65e175bSOded Gabbay 1372*e65e175bSOded Gabbay #endif /* GOYA_BLOCKS_H_ */ 1373