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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-xgene-sb.txt1 APM X-Gene Standby GPIO controller bindings
6 +-------
[all...]
H A Dgpio-xgene.txt1 APM X-Gene SoC GPIO controller bindings
7 - compatible: "apm,xgene-gpio" for X-Gene GPIO controller
8 - reg: Physical base address and size of the controller's registers
9 - #gpio-cells: Should be two.
10 - first cell is the pin number
11 - second cell is used to specify the gpio polarity:
14 - gpio-controller: Marks the device node as a GPIO controller.
18 compatible = "apm,xgene-gpio";
20 gpio-controller;
21 #gpio-cells = <2>;
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
16 Each PCIe node needs to have property msi-parent that points to an MSI
25 compatible = "apm,xgene1-msi";
[all …]
H A Dxgene-pci.txt1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
15 - dma-ranges: ranges for the inbound memory regions.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dapm-xgene-hwmon.txt1 APM X-Gene hwmon driver
3 APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox.
6 - compatible : should be "apm,xgene-slimpro-hwmon"
7 - mboxes : use the label reference for the mailbox as the first parameter.
12 compatible = "apm,xgene-slimpro-hwmon";
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dxgene-rtc.txt1 * APM X-Gene Real Time Clock
3 RTC controller for the APM X-Gene Real Time Clock
6 - compatible : Should be "apm,xgene-rtc"
7 - reg: physical base address of the controller and length of memory mapped
9 - interrupts: IRQ line for the RTC.
10 - #clock-cells: Should be 1.
11 - clocks: Reference to the clock entry.
16 compatible = "fixed-clock";
17 #clock-cells = <1>;
18 clock-frequency = <100000000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/rng/
H A Dapm,x-gene-rng.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rng/apm,x-gene-rng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC Random Number Generator
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-rng
26 - compatible
27 - clocks
28 - interrupts
[all …]
H A Dapm,rng.txt1 APM X-Gene SoC random number generator.
5 - compatible : should be "apm,xgene-rng"
6 - reg : specifies base physical address and size of the registers map
7 - clocks : phandle to clock-controller plus clock-specifier pair
8 - interrupts : specify the fault interrupt for the RNG device
13 compatible = "apm,xgene-rng";
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dapm-xgene-dma.txt1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
14 4th - Soc efuse register address space.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
H A Dapm-xgene-mdio.txt1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
6 - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
7 - #address-cells: Must be <1>.
8 - #size-cells: Must be <0>.
9 - reg: Address and length of the register set
10 - clocks: Reference to the clock entry
13 - compatible: PHY identifier. Please refer ./phy.txt for the format.
14 - reg: The ID number for the phy.
19 compatible = "apm,xgene-mdio-rgmii";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Dapm-xgene-pmu.txt1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
6 L3C - L3 cache controller
7 IOB - IO bridge
8 MCB - Memory controller bridge
9 MC - Memory controller
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
16 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
17 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-xgene-slimpro.txt1 APM X-Gene SLIMpro Mailbox I2C Driver
7 - compatible : should be "apm,xgene-slimpro-i2c"
8 - mboxes : use the label reference for the mailbox as the first parameter.
13 compatible = "apm,xgene-slimpro-i2c";
/freebsd/sys/contrib/device-tree/Bindings/arm/apm/
H A Dscu.txt1 APM X-GENE SoC series SCU Registers
7 - compatible : should contain two values. First value must be:
8 - "apm,xgene-scu"
11 - reg : offset and length of the register set.
14 scu: system-clk-controller@17000000 {
15 compatible = "apm,xgene-scu","syscon";
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
18 - #mbox-cells: only one to specify the mailbox channel number.
24 compatible = "apm,xgene-slimpro-mbox";
26 #mbox-cells = <1>;
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-mustang.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
10 /include/ "apm-storm.dtsi"
13 model = "APM X-Gene Mustang board";
14 compatible = "apm,mustang", "apm,xgene-storm";
23 gpio-keys {
24 compatible = "gpio-keys";
28 linux,input-type = <0x1>;
29 interrupt-parent = <&sbgpio>;
35 compatible = "apm,mustang-poweroff-mailbox", "syscon";
[all …]
H A Dapm-merlin.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
10 /include/ "apm-shadowcat.dtsi"
13 model = "APM X-Gene Merlin board";
14 compatible = "apm,merlin", "apm,xgene-shadowcat";
23 gpio-keys {
24 compatible = "gpio-keys";
28 linux,input-type = <0x1>;
29 interrupt-parent = <&sbgpio>;
35 compatible = "apm,merlin-poweroff-mailbox", "syscon";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
[all …]
/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dapm-xgene-edac.txt1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp1 //===- HexagonGenExtract.cpp ----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
33 static cl::opt<unsigned> ExtractCutoff("extract-cutoff", cl::init(~0U),
38 // One of the reasons for "extract" is to put a sequence of bits in a regis-
40 // "insert"). If the bits are already at offset 0, it is better not to gene-
43 static cl::opt<bool> NoSR0("extract-nosr0", cl::init(true), cl::Hidden,
46 static cl::opt<bool> NeedAnd("extract-needand", cl::init(true), cl::Hidden,
101 BasicBlock *BB = In->getParent(); in INITIALIZE_PASS_DEPENDENCY()
102 LLVMContext &Ctx = BB->getContext(); in INITIALIZE_PASS_DEPENDENCY()
[all …]
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha512-armv8.pl2 # Copyright 2014-2025 The OpenSSL Project Authors. All Rights Reserved.
23 # SHA256-hw SHA256(*) SHA512
24 # Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
25 # Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
26 # Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
28 # X-Gene 20.0 (+100%) 12.8 (+300%(***))
35 # (**) The result is a trade-off: it's possible to improve it by
37 # on Cortex-A53 (or by 4 cycles per round).
38 # (***) Super-impressive coefficients over gcc-generated code are
40 # generated with -mgeneral-regs-only is significantly faster
[all …]
H A Dsha1-armv8.pl2 # Copyright 2014-2025 The OpenSSL Project Authors. All Rights Reserved.
22 # hardware-assisted software(*)
24 # Cortex-A53 2.24 8.03 (+97%)
25 # Cortex-A57 2.35 7.88 (+74%)
27 # X-Gene 8.80 (+200%)
34 # optimizes compiler output at run-time.
42 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
43 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
44 die "can't locate arm-xlate.pl";
46 open OUT,"| \"$^X\" $xlate $flavour \"$output\""
[all …]
/freebsd/sys/crypto/openssl/aarch64/
H A Dsha256-armv8.S1 /* Do not modify. This file is auto-generated from sha512-armv8.pl. */
2 // Copyright 2014-2025 The OpenSSL Project Authors. All Rights Reserved.
23 // SHA256-hw SHA256(*) SHA512
24 // Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
25 // Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
26 // Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
28 // X-Gene 20.0 (+100%) 12.8 (+300%(***))
35 // (**) The result is a trade-off: it's possible to improve it by
37 // on Cortex-A53 (or by 4 cycles per round).
38 // (***) Super-impressive coefficients over gcc-generated code are
[all …]

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