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/linux/arch/powerpc/kernel/
H A Dvecemu.c267 vector128 *vrs; in emulate_altivec() local
280 vrs = current->thread.vr_state.vr; in emulate_altivec()
285 vaddfp(&vrs[vd], &vrs[va], &vrs[vb]); in emulate_altivec()
288 vsubfp(&vrs[vd], &vrs[va], &vrs[vb]); in emulate_altivec()
291 vrefp(&vrs[vd], &vrs[vb]); in emulate_altivec()
294 vrsqrtefp(&vrs[vd], &vrs[vb]); in emulate_altivec()
298 vrs[vd].u[i] = eexp2(vrs[vb].u[i]); in emulate_altivec()
302 vrs[vd].u[i] = elog2(vrs[vb].u[i]); in emulate_altivec()
306 vrs[vd].u[i] = rfin(vrs[vb].u[i]); in emulate_altivec()
310 vrs[vd].u[i] = rfiz(vrs[vb].u[i]); in emulate_altivec()
[all …]
H A Dsignal_64.c248 /* If VEC was enabled there are transactional VRs valid too, in setup_tm_sigcontexts()
249 * else they're a copy of the checkpointed VRs. in setup_tm_sigcontexts()
H A Dtm.S281 * After reclaiming, capture the checkpointed FPRs/VRs.
/linux/arch/arm/kernel/
H A Dunwind.c56 unsigned long vrs[16]; /* virtual register set */ member
243 ctrl->vrs[reg] = READ_ONCE_NOCHECK(*(*vsp)); in unwind_pop_register()
254 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; in unwind_exec_pop_subset_r4_to_r13()
266 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_subset_r4_to_r13()
275 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; in unwind_exec_pop_r4_to_rN()
287 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_r4_to_rN()
295 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; in unwind_exec_pop_subset_r0_to_r3()
306 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_subset_r0_to_r3()
345 ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; in unwind_exec_insn()
347 ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; in unwind_exec_insn()
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dnvidia,vrs-10.yaml4 $id: http://devicetree.org/schemas/rtc/nvidia,vrs-10.yaml#
13 NVIDIA VRS-10 (Voltage Regulator Specification) is a Power Management IC
18 and an interrupt controller for managing VRS events.
22 const: nvidia,vrs-10
52 compatible = "nvidia,vrs-10";
/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h141 #define PSTXSD(vrs, a, r, d) PREFIX_8LS(0xb8000000, vrs, a, r, d) argument
142 #define PSTXSSP(vrs, a, r, d) PREFIX_8LS(0xbc000000, vrs, a, r, d) argument
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3701.dtsi175 compatible = "nvidia,vrs-10";
178 /* VRS Wake ID is 24 */
H A Dtegra234-p3767.dtsi128 compatible = "nvidia,vrs-10";
131 /* VRS Wake ID is 24 */
/linux/Documentation/arch/loongarch/
H A Dintroduction.rst18 registers (FPRs), vector registers (VRs) and control status registers (CSRs)
78 VRs section in Registers
89 The VRs overlap with FPRs: for example, on a core implementing LSX and LASX,
91 ``$v0`` is shared with ``$f0``; same with all other VRs.
/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S51 .macro SAVE_VRS VRS OFFSET FRAME
53 stvx \VRS, 16, \FRAME
65 .macro RESTORE_VRS VRS OFFSET FRAME
67 lvx \VRS, 16, \FRAME
H A Dpoly1305-p10le_64.S68 .macro SAVE_VRS VRS OFFSET FRAME
70 stvx \VRS, 16, \FRAME
82 .macro RESTORE_VRS VRS OFFSET FRAME
84 lvx \VRS, 16, \FRAME
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum_router.h30 struct mlxsw_sp_vr *vrs; member
/linux/arch/s390/kvm/
H A Dkvm-s390.h29 save_vx_regs((__vector128 *)&run->s.regs.vrs); in kvm_s390_fpu_store()
38 load_vx_regs((__vector128 *)&run->s.regs.vrs); in kvm_s390_fpu_load()
/linux/drivers/regulator/
H A Dstm32-vrefbuf.c37 /* Matches resp. VRS = 000b, 001b, 010b, 011b */
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-power.json241 …ublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Duncore-power.json241 …ublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
/linux/arch/s390/include/asm/
H A Dfpu-insn-asm.h213 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-power.json254 …ublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-power.json255 …ublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
/linux/arch/s390/tools/
H A Dgen_opcode_table.c123 "VRS",
/linux/Documentation/arch/powerpc/
H A Dtransactional_memory.rst63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h294 * bit3: unlocks VDT, OVL, VRS, ?VRE?, VBS, VBE, LSR, EBR in nv_lock_vga_crtc_shadow()
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dintroduction.rst21 LoongArch的寄存器包括通用寄存器（GPRs）、浮點寄存器（FPRs）、向量寄存器（VRs）
/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst21 LoongArch的寄存器包括通用寄存器（GPRs）、浮点寄存器（FPRs）、向量寄存器（VRs）
/linux/drivers/rtc/
H A Drtc-nvidia-vrs10.c524 { .compatible = "nvidia,vrs-10" },

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