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/linux/include/soc/fsl/qe/
H A Ducc_fast.h3 * Internal header file for UCC FAST unit routines.
18 #include <soc/fsl/qe/ucc.h>
66 /* ucc_fast_channel_protocol_mode - UCC FAST mode */
86 /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
92 /* UCC fast diagnostic mode */
100 /* UCC fast Sync length (transparent mode only) */
108 /* UCC fast RTS mode */
114 /* UCC fast receiver decoding mode */
122 /* UCC fast transmitter encoding mode */
130 /* UCC fast CRC length */
[all …]
H A Ducc_slow.h9 * Internal header file for UCC SLOW unit routines.
19 #include <soc/fsl/qe/ucc.h>
80 /* UCC Slow Channel Protocol Mode */
87 /* UCC Slow Transparent Transmit CRC (TCRC) */
97 /* UCC Slow oversampling rate for transmitter (TDCR) */
109 /* UCC Slow Oversampling rate for receiver (RDCR)
122 /* UCC Slow Transmitter encoding method (TENC)
129 /* UCC Slow Receiver decoding method (RENC)
136 /* UCC Slow Diagnostic mode (DIAG)
186 struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
[all …]
H A Dimmap_qe.h236 /* QE UCC Slow */
252 u8 guemr; /* UCC general extended mode register */
255 /* QE UCC Fast */
267 __be32 urfb; /* UCC receive FIFO base */
268 __be16 urfs; /* UCC receive FIFO size */
270 __be16 urfet; /* UCC receive FIFO emergency threshold */
271 __be16 urfset; /* UCC receive FIFO special emergency
273 __be32 utfb; /* UCC transmit FIFO base */
274 __be16 utfs; /* UCC transmit FIFO size */
276 __be16 utfet; /* UCC transmit FIFO emergency threshold */
[all …]
H A Ducc.h9 * Internal header file for UCC unit routines.
29 * Sets UCC to slow or fast mode.
31 * ucc_num - (In) number of UCC (0-7).
32 * speed - (In) slow or fast mode for UCC.
47 /* QE MUX clock routing for UCC
H A Dqe.h415 * These values are for the UCC in the LSBs
594 /* UCC GUEMR register */
605 /* structure representing UCC SLOW parameter RAM */
626 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
676 /* General UCC FAST Mode Register */
696 /* UART Slow UCC Event Register (UCCE) */
707 /* HDLC Slow UCC Event Register (UCCE) */
719 /* BISYNC Slow UCC Event Register (UCCE) */
727 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
761 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-ucc-qmc.yaml4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
35 description: UCC interrupt line in the QE interrupt controller
78 - fsl,mpc8321-ucc-qmc-hdlc
79 - const: fsl,qe-ucc-qmc-hdlc
155 compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";
188 compatible = "fsl,mpc8321-ucc-qmc-hdlc",
189 "fsl,qe-ucc-qmc-hdlc",
H A Duqe_serial.txt4 compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
5 "fsl,t1040-ucc-uart".
6 port-number : port number of UCC-UART
12 ucc_serial: ucc@2200 {
13 compatible = "fsl,t1040-ucc-uart";
H A Dfsl,ucc-hdlc.yaml4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
16 const: fsl,ucc-hdlc
120 compatible = "fsl,ucc-hdlc";
136 compatible = "fsl,ucc-hdlc";
/linux/drivers/net/ethernet/freescale/
H A Ducc_geth.h8 * Internal header file for UCC Gigabit Ethernet unit routines.
24 #include <soc/fsl/qe/ucc.h>
27 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
53 u32 uempr; /* UCC Ethernet Mac parameter reg */
54 u32 utbipar; /* UCC tbi address reg */
55 u16 uescr; /* UCC Ethernet statistics control reg */
95 never even reach the UCC */
107 /* UCC GETH TEMODR Register */
121 /* UCC GETH TEMODR Register */
157 /* UCC GETH Event Register */
[all …]
/linux/drivers/soc/fsl/qe/
H A Ducc_slow.c9 * QE UCC Slow API Set - UCC Slow specific routines implementations.
23 #include <soc/fsl/qe/ucc.h>
80 /* Enable reception and/or transmission on this UCC. */ in ucc_slow_enable()
101 /* Disable reception and/or transmission on this UCC. */ in ucc_slow_disable()
115 /* Initialize the UCC for Slow operations
133 /* check if the UCC port number is in range. */ in ucc_slow_init()
135 printk(KERN_ERR "%s: illegal UCC number\n", __func__); in ucc_slow_init()
161 /* Fill slow UCC structure */ in ucc_slow_init()
166 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); in ucc_slow_init()
189 /* Set UCC to slow type */ in ucc_slow_init()
[all …]
H A Ducc_fast.c9 * QE UCC Fast API Set - UCC Fast specific routines implementations.
23 #include <soc/fsl/qe/ucc.h>
28 printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num); in ucc_fast_dump_regs()
100 /* Enable reception and/or transmission on this UCC. */ in ucc_fast_enable()
121 /* Disable reception and/or transmission on this UCC. */ in ucc_fast_disable()
145 /* check if the UCC port number is in range. */ in ucc_fast_init()
147 printk(KERN_ERR "%s: illegal UCC number\n", __func__); in ucc_fast_init()
203 /* Fill fast UCC structure */ in ucc_fast_init()
208 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); in ucc_fast_init()
229 /* Set UCC to fast type */ in ucc_fast_init()
[all …]
H A Ducc.c3 * arch/powerpc/sysdev/qe_lib/ucc.c
5 * QE UCC API Set - UCC specific routines implementations.
21 #include <soc/fsl/qe/ucc.h>
45 /* Configure the UCC to either Slow or Fast.
47 * A given UCC can be figured to support either "slow" devices (e.g. UART)
50 * 'ucc_num' is the UCC number, from 0 - 7.
104 /* check if the UCC number is in range. */ in ucc_mux_set_grant_tsa_bkpt()
127 /* check if the UCC number is in range. */ in ucc_set_qe_mux_rxtx()
203 /* Check for invalid combination of clock and UCC number */ in ucc_set_qe_mux_rxtx()
H A DKconfig22 This option provides qe_lib support to UCC slow
29 This option provides qe_lib support to UCC fast
32 config UCC config
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt1 * UCC (Unified Communications Controllers)
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
22 - rx-clock-name: the UCC receive clock source
26 - tx-clock-name: the UCC transmit clock source
35 - rx-clock : represents the UCC receive clock source.
39 - tx-clock: represents the UCC transmit clock source;
55 ucc@2000 {
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts253 enet0: ucc@2000 {
269 compatible = "fsl,ucc-mdio";
306 compatible = "fsl,ucc-mdio";
317 compatible = "fsl,ucc-mdio";
324 enet2: ucc@2200 {
340 compatible = "fsl,ucc-mdio";
347 enet1: ucc@3000 {
363 compatible = "fsl,ucc-mdio";
370 enet3: ucc@3200 {
386 compatible = "fsl,ucc-mdio";
[all …]
H A Dmpc8569si-post.dtsi250 ucc@2000 {
257 ucc@2200 {
264 ucc@3000 {
271 ucc@3200 {
278 ucc@3400 {
285 ucc@3600 {
H A Dp1021si-post.dtsi201 ucc@2000 {
212 compatible = "fsl,ucc-mdio";
215 ucc@2400 {
222 ucc@2600 {
229 ucc@2200 {
H A Dt104xd4rdb.dtsi232 ucc_hdlc: ucc@2000 {
233 compatible = "fsl,ucc-hdlc";
246 ucc_serial: ucc@2200 {
247 compatible = "fsl,t1040-ucc-uart";
H A Dt104xrdb.dtsi242 ucc_hdlc: ucc@2000 {
243 compatible = "fsl,ucc-hdlc";
256 ucc_serial: ucc@2200 {
257 compatible = "fsl,t1040-ucc-uart";
/linux/arch/powerpc/platforms/85xx/
H A Dcommon.c96 struct device_node *ucc; in mpc85xx_qe_par_io_init() local
101 for_each_node_by_name(ucc, "ucc") in mpc85xx_qe_par_io_init()
102 par_io_of_config(ucc); in mpc85xx_qe_par_io_init()
/linux/drivers/dma/ti/
H A Dk3-udma.c865 struct udma_chan_config *ucc = &uc->config; in udma_start_desc() local
867 if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode && in udma_start_desc()
868 (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) { in udma_start_desc()
4134 struct udma_chan_config *ucc; in udma_dma_filter_fn() local
4146 ucc = &uc->config; in udma_dma_filter_fn()
4162 ucc->remote_thread_id = filter_param->remote_thread_id; in udma_dma_filter_fn()
4163 ucc->atype = filter_param->atype; in udma_dma_filter_fn()
4164 ucc->asel = filter_param->asel; in udma_dma_filter_fn()
4165 ucc->tr_trigger_type = filter_param->tr_trigger_type; in udma_dma_filter_fn()
4167 if (ucc->tr_trigger_type) { in udma_dma_filter_fn()
[all …]
/linux/drivers/net/wan/
H A Dfsl_ucc_hdlc.h16 #include <soc/fsl/qe/ucc.h>
19 /* UCC HDLC event register */
72 struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
/linux/drivers/tty/serial/
H A Ducc_uart.c184 unsigned int ucc_num; /* First ucc is 0, not 1 */
307 * interrupt when the UCC is finished sending characters.
479 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); in qe_uart_int_rx()
635 * Initialize a UCC for UART.
637 * This function configures a given UCC to be used as a UART device. Basic
638 * UCC initialization is handled in qe_uart_request_port(). This function
649 /* First, disable TX and RX in the UCC */ in qe_uart_init_ucc()
652 /* Program the UCC UART parameter RAM */ in qe_uart_init_ucc()
781 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", in qe_uart_startup()
973 dev_err(port->dev, "could not initialize UCC%u\n", in qe_uart_request_port()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc836x_rdk.dts264 enet0: ucc@2000 {
279 enet1: ucc@3000 {
294 enet2: ucc@2600 {
309 enet3: ucc@3200 {
327 compatible = "fsl,ucc-mdio";
351 serial2: ucc@2400 {
364 serial3: ucc@3400 {
H A Dkmeter1.dts315 enet_estar1: ucc@2000 {
331 enet_estar2: ucc@3000 {
347 enet_piggy2: ucc@3200 {
363 enet_eth1: ucc@2400 {
379 enet_eth2: ucc@3400 {
395 enet_eth3: ucc@2600 {
411 enet_eth4: ucc@3600 {
430 compatible = "fsl,ucc-mdio";

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