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/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Duart-routing.yaml17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
24 which owns the system configuration policy, to configure how UARTs and
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h156 /* UARTs */
233 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
235 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
236 /* UARTs are driven by internal divided clock */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
/linux/drivers/tty/serial/8250/
H A D8250_pxa.c3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
169 MODULE_DESCRIPTION("driver for PXA on-board UARTS");
/linux/include/uapi/linux/
H A Dserial_core.h27 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
146 /* Altera UARTs */
H A Dserial_reg.h98 some Freescale UARTs) */
239 * The Intel XScale on-chip UARTs define these bits
348 * Extra serial register definitions for the internal UARTs
/linux/arch/mips/include/asm/mach-rc32434/
H A Dirq.h17 /* 16550 UARTs */
/linux/include/linux/ssb/
H A Dssb_driver_extif.h11 * support external devices such as UARTs and the BCM2019 Bluetooth
13 * The external interface core also contains 2 on-chip 16550 UARTs, clock
H A Dssb_driver_chipcommon.h8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
29 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
/linux/arch/arm/mach-s3c/
H A Ddev-uart-s3c64xx.c25 /* 64xx uarts are closer together */
H A Dpm-common.c43 * restore the UARTs state yet
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dstarfive,jh7110-sys-pinctrl.yaml16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
/linux/arch/mips/alchemy/common/
H A Dplatform.c131 printk(KERN_INFO "Alchemy: missing support for UARTs\n"); in alchemy_setup_uarts()
136 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); in alchemy_setup_uarts()
/linux/Documentation/driver-api/serial/
H A Dserial-iso7816.rst14 Some CPUs/UARTs (e.g., Microchip AT91) contain a built-in mode capable of
/linux/arch/sparc/include/asm/
H A Dns87303.h57 /* Tape UARTs and Parallel Port Config Register (TUP) bits */
/linux/drivers/acpi/x86/
H A Dutils.c509 /* For PCI UARTs without an UID */ in acpi_dmi_skip_serdev_enumeration()
514 * Devfn values for PCI UARTs on Bay Trail SoCs, which are in acpi_dmi_skip_serdev_enumeration()
527 /* PNP enumerated UARTs */ in acpi_dmi_skip_serdev_enumeration()
/linux/arch/arm/mach-lpc32xx/
H A Dserial.c106 /* Setup UART clock modes for all UARTs, disable autoclock */ in lpc32xx_serial_init()
/linux/arch/powerpc/boot/dts/
H A DkuroboxHD.dts56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
H A DkuroboxHG.dts56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt5 synchronous/asynchronous NOR, FPGA, UARTS and more.
/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
25 #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
/linux/arch/arm/mach-omap1/
H A Dserial.c48 * Internal UARTs need to be initialized for the 8250 autoconfig to work
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-wega.dtsi176 /* UARTs */
H A Dam335x-pcm-953.dtsi177 /* UARTs */
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-gateworks-gw2348.dts106 * FIXME: Latch LEDs or extra UARTs at CS4

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