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/freebsd/sys/dev/gve/
H A Dgve_tx_dqo.c38 gve_unmap_packet(struct gve_tx_ring *tx, in gve_unmap_packet() argument
41 bus_dmamap_sync(tx->dqo.buf_dmatag, pending_pkt->dmamap, in gve_unmap_packet()
43 bus_dmamap_unload(tx->dqo.buf_dmatag, pending_pkt->dmamap); in gve_unmap_packet()
47 gve_free_tx_mbufs_dqo(struct gve_tx_ring *tx) in gve_free_tx_mbufs_dqo() argument
52 for (i = 0; i < tx->dqo.num_pending_pkts; i++) { in gve_free_tx_mbufs_dqo()
53 pending_pkt = &tx->dqo.pending_pkts[i]; in gve_free_tx_mbufs_dqo()
57 if (gve_is_qpl(tx->com.priv)) { in gve_free_tx_mbufs_dqo()
61 gve_unmap_packet(tx, pending_pkt); in gve_free_tx_mbufs_dqo()
71 struct gve_tx_ring *tx = &priv->tx[i]; in gve_tx_free_ring_dqo() local
74 if (tx->dqo.desc_ring != NULL) { in gve_tx_free_ring_dqo()
[all …]
H A Dgve_tx.c38 gve_tx_fifo_init(struct gve_priv *priv, struct gve_tx_ring *tx) in gve_tx_fifo_init() argument
40 struct gve_queue_page_list *qpl = tx->com.qpl; in gve_tx_fifo_init()
41 struct gve_tx_fifo *fifo = &tx->fifo; in gve_tx_fifo_init()
54 struct gve_tx_ring *tx = &priv->tx[i]; in gve_tx_free_ring_gqi() local
56 if (tx->desc_ring != NULL) { in gve_tx_free_ring_gqi()
57 gve_dma_free_coherent(&tx->desc_ring_mem); in gve_tx_free_ring_gqi()
58 tx->desc_ring = NULL; in gve_tx_free_ring_gqi()
61 if (tx->info != NULL) { in gve_tx_free_ring_gqi()
62 free(tx->info, M_GVE); in gve_tx_free_ring_gqi()
63 tx->info = NULL; in gve_tx_free_ring_gqi()
[all …]
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dtxg.c122 tx_state_t *tx = &dp->dp_tx; in txg_init() local
124 memset(tx, 0, sizeof (tx_state_t)); in txg_init()
126 tx->tx_cpu = vmem_zalloc(max_ncpus * sizeof (tx_cpu_t), KM_SLEEP); in txg_init()
131 mutex_init(&tx->tx_cpu[c].tc_lock, NULL, MUTEX_DEFAULT, NULL); in txg_init()
132 mutex_init(&tx->tx_cpu[c].tc_open_lock, NULL, MUTEX_NOLOCKDEP, in txg_init()
135 cv_init(&tx->tx_cpu[c].tc_cv[i], NULL, CV_DEFAULT, in txg_init()
137 list_create(&tx->tx_cpu[c].tc_callbacks[i], in txg_init()
143 mutex_init(&tx->tx_sync_lock, NULL, MUTEX_DEFAULT, NULL); in txg_init()
145 cv_init(&tx->tx_sync_more_cv, NULL, CV_DEFAULT, NULL); in txg_init()
146 cv_init(&tx in txg_init()
160 tx_state_t *tx = &dp->dp_tx; txg_fini() local
198 tx_state_t *tx = &dp->dp_tx; txg_sync_start() local
223 txg_thread_enter(tx_state_t * tx,callb_cpr_t * cpr) txg_thread_enter() argument
230 txg_thread_exit(tx_state_t * tx,callb_cpr_t * cpr,kthread_t ** tpp) txg_thread_exit() argument
241 txg_thread_wait(tx_state_t * tx,callb_cpr_t * cpr,kcondvar_t * cv,clock_t time) txg_thread_wait() argument
261 tx_state_t *tx = &dp->dp_tx; txg_sync_stop() local
319 tx_state_t *tx = &dp->dp_tx; txg_hold_open() local
388 tx_state_t *tx = &dp->dp_tx; txg_quiesce() local
451 tx_state_t *tx = &dp->dp_tx; txg_dispatch_callbacks() local
495 tx_state_t *tx = &dp->dp_tx; txg_wait_callbacks() local
504 tx_state_t *tx = &dp->dp_tx; txg_is_quiescing() local
512 tx_state_t *tx = &dp->dp_tx; txg_has_quiesced_to_sync() local
522 tx_state_t *tx = &dp->dp_tx; txg_sync_thread() local
612 tx_state_t *tx = &dp->dp_tx; txg_quiesce_thread() local
667 tx_state_t *tx = &dp->dp_tx; txg_delay() local
695 tx_state_t *tx = &dp->dp_tx; txg_wait_synced_impl() local
756 tx_state_t *tx = &dp->dp_tx; txg_wait_open() local
793 tx_state_t *tx = &dp->dp_tx; txg_kick() local
811 tx_state_t *tx = &dp->dp_tx; txg_stalled() local
818 tx_state_t *tx = &dp->dp_tx; txg_sync_waiting() local
[all...]
H A Ddmu_tx.c43 typedef void (*dmu_tx_hold_func_t)(dmu_tx_t *tx, struct dnode *dn,
67 dmu_tx_t *tx = kmem_zalloc(sizeof (dmu_tx_t), KM_SLEEP); in dmu_tx_create_dd() local
68 tx->tx_dir = dd; in dmu_tx_create_dd()
70 tx->tx_pool = dd->dd_pool; in dmu_tx_create_dd()
71 list_create(&tx->tx_holds, sizeof (dmu_tx_hold_t), in dmu_tx_create_dd()
73 list_create(&tx->tx_callbacks, sizeof (dmu_tx_callback_t), in dmu_tx_create_dd()
75 tx->tx_start = gethrtime(); in dmu_tx_create_dd()
76 return (tx); in dmu_tx_create_dd()
82 dmu_tx_t *tx = dmu_tx_create_dd(os->os_dsl_dataset->ds_dir); in dmu_tx_create() local
83 tx->tx_objset = os; in dmu_tx_create()
[all …]
H A Ddsl_destroy.c91 dsl_destroy_snapshot_check(void *arg, dmu_tx_t *tx) in dsl_destroy_snapshot_check() argument
97 dsl_pool_t *dp = dmu_tx_pool(tx); in dsl_destroy_snapshot_check()
128 process_old_cb(void *arg, const blkptr_t *bp, boolean_t bp_freed, dmu_tx_t *tx) in process_old_cb() argument
137 dsl_deadlist_insert(&poa->ds->ds_deadlist, bp, bp_freed, tx); in process_old_cb()
148 dsl_free_sync(poa->pio, dp, tx->tx_txg, bp); in process_old_cb()
155 dsl_dataset_t *ds_next, boolean_t after_branch_point, dmu_tx_t *tx) in process_old_deadlist() argument
170 process_old_cb, &poa, tx)); in process_old_deadlist()
176 -poa.used, -poa.comp, -poa.uncomp, tx); in process_old_deadlist()
205 dsl_dir_remove_clones_key_impl(dsl_dir_t *dd, uint64_t mintxg, dmu_tx_t *tx, in dsl_dir_remove_clones_key_impl() argument
231 mintxg, tx); in dsl_dir_remove_clones_key_impl()
[all …]
H A Ddmu_object.c49 int dnodesize, dnode_t **allocated_dnode, const void *tag, dmu_tx_t *tx) in dmu_object_alloc_impl() argument
193 bonuslen, dn_slots, tx); in dmu_object_alloc_impl()
195 dmu_tx_add_new_object(tx, dn); in dmu_object_alloc_impl()
227 dmu_object_type_t bonustype, int bonuslen, dmu_tx_t *tx) in dmu_object_alloc() argument
230 bonuslen, 0, NULL, NULL, tx); in dmu_object_alloc()
236 dmu_tx_t *tx) in dmu_object_alloc_ibs() argument
239 bonustype, bonuslen, 0, NULL, NULL, tx); in dmu_object_alloc_ibs()
244 dmu_object_type_t bonustype, int bonuslen, int dnodesize, dmu_tx_t *tx) in dmu_object_alloc_dnsize() argument
247 bonuslen, dnodesize, NULL, NULL, tx)); in dmu_object_alloc_dnsize()
258 int dnodesize, dnode_t **allocated_dnode, const void *tag, dmu_tx_t *tx) in dmu_object_alloc_hold() argument
[all …]
H A Ddsl_dataset.c104 uint64_t obj, dmu_tx_t *tx);
106 dmu_tx_t *tx);
137 dsl_dataset_block_born(dsl_dataset_t *ds, const blkptr_t *bp, dmu_tx_t *tx) in dsl_dataset_block_born() argument
139 spa_t *spa = dmu_tx_pool(tx)->dp_spa; in dsl_dataset_block_born()
148 ASSERT(dmu_tx_is_syncing(tx)); in dsl_dataset_block_born()
155 dsl_pool_mos_diduse_space(tx->tx_pool, in dsl_dataset_block_born()
162 dmu_buf_will_dirty(ds->ds_dbuf, tx); in dsl_dataset_block_born()
206 DD_USED_REFRSRV, DD_USED_HEAD, tx); in dsl_dataset_block_born()
218 uint64_t size, uint64_t birth, dmu_tx_t *tx) in dsl_dataset_block_remapped() argument
222 ASSERT(dmu_tx_is_syncing(tx)); in dsl_dataset_block_remapped()
[all …]
/freebsd/sys/dev/ioat/
H A Dioat_test.c83 ioat_test_transaction_destroy(struct test_transaction *tx) in ioat_test_transaction_destroy() argument
88 if (tx->buf[i] != NULL) { in ioat_test_transaction_destroy()
89 free(tx->buf[i], M_IOAT_TEST); in ioat_test_transaction_destroy()
90 tx->buf[i] = NULL; in ioat_test_transaction_destroy()
94 free(tx, M_IOAT_TEST); in ioat_test_transaction_destroy()
101 struct test_transaction *tx; in ioat_test_transaction_destroy()
104 tx = malloc(sizeof(*tx), M_IOAT_TEST, M_NOWAIT | M_ZERO); in ioat_test_transaction_create()
105 if (tx == NULL) in ioat_test_transaction_create()
108 tx in ioat_test_transaction_create()
107 struct test_transaction *tx; ioat_test_transaction_create() local
146 ioat_compare_ok(struct test_transaction * tx) ioat_compare_ok() argument
180 struct test_transaction *tx; ioat_dma_test_callback() local
206 struct test_transaction *tx; ioat_test_prealloc_memory() local
237 struct test_transaction *tx, *s; ioat_test_release_memory() local
251 struct test_transaction *tx; ioat_test_submit_1_tx() local
[all...]
/freebsd/sys/dev/wtap/
H A Dif_wtapioctl.h60 u_int32_t ast_txurn; /* tx underrun interrupts */
67 u_int32_t ast_tx_encap; /* tx encapsulation failed */
68 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
69 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
70 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
71 u_int32_t ast_tx_linear; /* tx linearized to cluster */
72 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
73 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
74 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
75 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
[all …]
/freebsd/sys/dev/mlx5/mlx5_accel/
H A Dmlx5_ipsec_fs.c48 * TX tables are organized differently for Ethernet and for RoCE:
51 * Ethernet Tx | SA KSPI | match
56 * DROP<--------+ |---->|Encrypt|------>|Flowtable|---->| TX NS |
61 * Tx |Flowtable|----->|Flowtable|---->+ |
630 static int ipsec_counter_rule_tx(struct mlx5_core_dev *mdev, struct mlx5e_ipsec_tx *tx) in ipsec_counter_rule_tx() argument
642 dest.counter_id = mlx5_fc_id(tx->fc->cnt); in ipsec_counter_rule_tx()
643 fte = mlx5_add_flow_rules(tx->ft.status, NULL, &flow_act, &dest, 1); in ipsec_counter_rule_tx()
646 mlx5_core_err(mdev, "Fail to add ipsec tx counter rule err=%d\n", err); in ipsec_counter_rule_tx()
650 tx->status.rule = fte; in ipsec_counter_rule_tx()
657 static void tx_destroy_roce(struct mlx5e_ipsec_tx *tx) { in tx_destroy_roce() argument
[all …]
/freebsd/sys/dev/ath/
H A Dif_athioctl.h65 u_int32_t ast_txurn; /* tx underrun interrupts */
72 u_int32_t ast_tx_encap; /* tx encapsulation failed */
73 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
74 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
75 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
76 u_int32_t ast_tx_linear; /* tx linearized to cluster */
77 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
78 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
79 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
80 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dtx.h11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
32 * @TX_CMD_FLG_CALIB: activate PA TX power calibrations
73 * enum iwl_tx_cmd_flags - bitmasks for tx_flags in TX command for 22000
74 * @IWL_TX_FLAGS_CMD_RATE: use rate from the TX command
93 * enum iwl_tx_pm_timeouts - pm timeout values in TX command
109 * enum iwl_tx_cmd_sec_ctrl - bitmasks for security control in TX command
117 * from the table instead of from the TX comman
741 struct iwl_tx_cmd tx; global() member
760 struct iwl_tx_cmd tx; global() member
[all...]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.h44 #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
45 #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
46 #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
47 #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
53 #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
57 #define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
152 #define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */
153 #define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */
154 #define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */
155 #define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */
[all …]
/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-x86_64.pl166 my @TX=("%rax","%rbx");
180 xor $TX[1],$TX[1]
182 sub $XX[0],$TX[1]
184 movl ($dat,$XX[0],4),$TX[0]#d
189 and \$7,$TX[1]
192 sub $TX[1],$len
194 add $TX[0]#b,$YY#b
196 movl $TX[0]#d,($dat,$YY,4)
198 add $TY#b,$TX[0]#b
200 movl ($dat,$TX[0],4),$TY#d
[all …]
/freebsd/sys/dev/e1000/
H A De1000_regs.h90 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
103 #define E1000_TCTL 0x00400 /* Tx Control - RW */
104 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
105 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
106 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
117 #define E1000_IOSFPC 0x00F28 /* TX corrupted data */
193 /* QAV Tx mode control register */
196 /* QAV Tx mode control register bitfields masks */
221 /* QAV Tx mode control registers where _n can be 0 or 1. */
224 /* QAV Tx mode control register bitfields masks */
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dtestmode.h26 * @MT76_TM_ATTR_TX_LENGTH: packet tx mpdu length (u32)
27 * @MT76_TM_ATTR_TX_RATE_MODE: packet tx mode (u8, see &enum mt76_testmode_tx_mode)
28 * @MT76_TM_ATTR_TX_RATE_NSS: packet tx number of spatial streams (u8)
29 * @MT76_TM_ATTR_TX_RATE_IDX: packet tx rate/MCS index (u8)
30 * @MT76_TM_ATTR_TX_RATE_SGI: packet tx use short guard interval (u8)
31 * @MT76_TM_ATTR_TX_RATE_LDPC: packet tx enable LDPC (u8)
32 * @MT76_TM_ATTR_TX_RATE_STBC: packet tx enable STBC (u8)
33 * @MT76_TM_ATTR_TX_LTF: packet tx LTF, set 0 to 2 for 1x, 2x, and 4x LTF (u8)
35 * @MT76_TM_ATTR_TX_ANTENNA: tx antenna mask (u8)
36 * @MT76_TM_ATTR_TX_POWER_CONTROL: enable tx power control (u8)
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212desc.h27 * AR5212-specific tx/rx descriptor definition.
40 } tx; member
50 #define ds_ctl2 u.tx.ctl2
51 #define ds_ctl3 u.tx.ctl3
52 #define ds_txstatus0 u.tx.status0
53 #define ds_txstatus1 u.tx.status1
57 /* TX ds_ctl0 */
65 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
67 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
71 /* TX ds_ctl1 */
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos.c262 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); in eqos_setup_txdesc()
263 sc->tx.desc_ring[index].des0 = htole32((uint32_t)paddr); in eqos_setup_txdesc()
264 sc->tx.desc_ring[index].des1 = htole32((uint32_t)(paddr >> 32)); in eqos_setup_txdesc()
265 sc->tx.desc_ring[index].des2 = htole32(tdes2 | len); in eqos_setup_txdesc()
266 sc->tx.desc_ring[index].des3 = htole32(tdes3 | total_len); in eqos_setup_txdesc()
273 int first = sc->tx.head; in eqos_setup_txbuf()
277 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, in eqos_setup_txbuf()
278 sc->tx.buf_map[first].map, m, segs, &nsegs, 0); in eqos_setup_txbuf()
282 device_printf(sc->dev, "TX packet too big trying defrag\n"); in eqos_setup_txbuf()
283 bus_dmamap_unload(sc->tx.buf_tag, sc->tx.buf_map[first].map); in eqos_setup_txbuf()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7280-herobrine-villager-r1.dtsi26 "TX SWR_ADC0", "ADC1_OUTPUT",
27 "TX SWR_ADC1", "ADC2_OUTPUT",
28 "TX SWR_ADC2", "ADC3_OUTPUT",
29 "TX SWR_DMIC0", "DMIC1_OUTPUT",
30 "TX SWR_DMIC1", "DMIC2_OUTPUT",
31 "TX SWR_DMIC2", "DMIC3_OUTPUT",
32 "TX SWR_DMIC3", "DMIC4_OUTPUT",
33 "TX SWR_DMIC4", "DMIC5_OUTPUT",
34 "TX SWR_DMIC5", "DMIC6_OUTPUT",
35 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
/freebsd/sys/contrib/openzfs/module/os/linux/zfs/
H A Dzfs_vnops_os.c97 * zfs_zinactive() may require a new tx, which could deadlock the system
98 * if you were already holding one. This deadlock occurs because the tx
100 * prevents the new tx from progressing, resulting in a deadlock. If you
101 * must call zrele() within a tx, use zfs_zrele_async(). Note that iput()
117 * the tx assigns, and sometimes after (e.g. z_lock), then failing
121 * Thread B is in an already-assigned tx, and blocks for this lock.
123 * forever, because the previous txg can't quiesce until B's tx commits.
138 * (6) At the end of each vnode op, the DMU tx must always commit,
150 * tx = dmu_tx_create(...); // get DMU tx
152 * error = dmu_tx_assign(tx, (waited ? TXG_NOTHROTTLE : 0) | TXG_NOWAIT);
[all …]
/freebsd/sys/dev/neta/
H A Dif_mvneta.c111 /* Rx/Tx Queue Control */
159 /* Tx Subroutines */
296 "tx_good_oct", "Good Octets Tx"},
298 "tx_good_frame", "Good Frames Tx"},
302 "tx_mcast_frame", "Multicast Frames Tx"},
304 "tx_bcast_frame", "Broadcast Frames Tx"},
308 "fc_tx", "Flow Control Tx"},
416 * Create Tx DMA in mvneta_dma_create()
434 "Failed to create DMA tag for Tx descriptors.\n"); in mvneta_dma_create()
451 "Failed to create DMA tag for Tx mbufs.\n"); in mvneta_dma_create()
[all …]
/freebsd/sys/contrib/openzfs/include/sys/
H A Ddmu_tx.h50 * No synchronization is needed because a tx can only be handled
116 * Used for dmu tx kstat.
145 int dmu_tx_assign(dmu_tx_t *tx, uint64_t txg_how);
146 void dmu_tx_commit(dmu_tx_t *tx);
147 void dmu_tx_abort(dmu_tx_t *tx);
148 uint64_t dmu_tx_get_txg(dmu_tx_t *tx);
149 struct dsl_pool *dmu_tx_pool(dmu_tx_t *tx);
150 void dmu_tx_wait(dmu_tx_t *tx);
161 int dmu_tx_is_syncing(dmu_tx_t *tx);
162 int dmu_tx_private_ok(dmu_tx_t *tx);
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscu_bios_definitions.h230 * Spread Spectrum Clocking (SSC) setting for Tx:
303 * AFE XCVR Tx Amplitude and Equalization Control Register Set
310 * - Software sets AFE XCVR Tx Control Register Tx Equalization
315 * LUTSel=00b. It contains the Tx Equalization settings that will be
322 * LUTSel=01b. It contains the Tx Equalization settings that will
329 * LUTSel=10b. It contains the Tx Equalization settings that will
336 * LUTSel=11b. It contains the Tx Equalization settings that will
393 * This bitfield indicates the OEM's desired default Tx
400 * SATA SSC Tx Disabled = 0x0
401 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgereg.h55 #define VGE_TXCTL 0x07 /* TX control register */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
88 #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
92 #define VGE_TXQTIMER 0x3E /* TX queue timer pend register */
94 #define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
95 #define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
96 #define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
97 #define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
99 #define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */
[all …]
/freebsd/tools/tools/ath/athalq/
H A Dar5416_ds.c50 MF(txs.u.tx.status[9], AR_TxDone), in ar5416_decode_txstatus()
51 MF(txs.u.tx.status[1], AR_FrmXmitOK), in ar5416_decode_txstatus()
52 MF(txs.u.tx.status[1], AR_Filtered), in ar5416_decode_txstatus()
53 txs.u.tx.status[2]); in ar5416_decode_txstatus()
57 MS(txs.u.tx.status[0], AR_TxRSSIAnt00), in ar5416_decode_txstatus()
58 MS(txs.u.tx.status[0], AR_TxRSSIAnt01), in ar5416_decode_txstatus()
59 MS(txs.u.tx.status[0], AR_TxRSSIAnt02)); in ar5416_decode_txstatus()
63 MS(txs.u.tx.status[5], AR_TxRSSIAnt10), in ar5416_decode_txstatus()
64 MS(txs.u.tx.status[5], AR_TxRSSIAnt11), in ar5416_decode_txstatus()
65 MS(txs.u.tx.status[5], AR_TxRSSIAnt12), in ar5416_decode_txstatus()
[all …]

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