| /freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/ |
| H A D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | fsl,imx8qxp-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
20 format and can map the input to VESA or JEIDA standards. The two channels
22 them to use. Two LDB channels from two LDB instances can work together in
23 LDB split mode to support a dual link LVDS display. The channel indexes
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|
| H A D | fsl,imx8qxp-pixel-combiner.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
14 single display controller and manipulates the two streams to support a number
16 either one screen, two screens, or virtual screens. The pixel combiner is
18 output channel.
23 - fsl,imx8qm-pixel-combiner
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|
| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
7 nodes describing each of the two LVDS encoder channels of the bridge.
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
15 interfaces as input for each LVDS channel.
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | renesas,drif.txt | 1 Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
2 ------------------------------------------------------------
4 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
7 +---------------------+ +---------------------+
8 | |-----SCK------->|CLK |
9 | Master |-----SS-------->|SYNC DRIFn (slave) |
10 | |-----SD0------->|D0 |
11 | |-----SD1------->|D1 |
12 +---------------------+ +---------------------+
14 As per datasheet, each DRIF channel (drifn) is made up of two internal
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|
| H A D | renesas,drif.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | arm,mhuv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
16 communication with remote processor(s), where the number of channel windows
21 between two processing elements to provide bidirectional communication, these
22 must be specified as two separate mailboxes.
33 - Data-transfer: Each transfer is made of one or more words, using one or more
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|
| H A D | fsl,mu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The Messaging Unit module enables two processors within the SoC to
21 other. The MU accomplishes synchronization using two sets of matching
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | qcom,pm8xxx-xoadc.txt | 8 - compatible: should be one of:
9 "qcom,pm8018-adc"
10 "qcom,pm8038-adc"
11 "qcom,pm8058-adc"
12 "qcom,pm8921-adc"
14 - reg: should contain the ADC base address in the PMIC, typically
17 - xoadc-ref-supply: should reference a regulator that can supply
22 iio-bindings.txt for more details, but notice that this particular
23 ADC has a special addressing scheme that require two cells for
24 identifying each ADC channel:
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|
| H A D | xilinx-xadc.txt | 7 The XADC has a DRP interface for communication. Currently two different
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
33 when using the axi-xadc or the axi-system-management-wizard this must be
37 - xlnx,external-mux:
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|
| H A D | st,stm32-dfsdm-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
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|
| H A D | adc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Cameron <jic23@kernel.org>
17 pattern: "^channel(@[0-9a-f]+)?$"
19 A channel index should match reg.
25 description: Unique name to identify which channel this is.
29 description: If provided, the channel is to be used in bipolar mode.
31 diff-channels:
32 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | nvm-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_regulatory_and_nvm_subcmd_ids - regulatory/NVM commands
61 * enum iwl_nvm_access_op - NVM access opcode
71 * enum iwl_nvm_access_target - target of the NVM_ACCESS_CMD
83 * enum iwl_nvm_section_type - section types for NVM_ACCESS_CMD
105 * struct iwl_nvm_access_cmd - Request the device to send an NVM section
123 * struct iwl_nvm_access_resp - response to NVM_ACCESS_CMD
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|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | fsl,ssi.txt | 4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
21 - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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|
| H A D | cs53l30.txt | 5 - compatible : "cirrus,cs53l30"
7 - reg : the I2C address of the device
9 - VA-supply, VP-supply : power supplies for the device,
14 - reset-gpios : a GPIO spec for the reset pin.
16 - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either
20 - cirru
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| H A D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
15 the core. The core expects two dma channels if both transmit and receive are
16 enabled, one channel otherwise.
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
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| /freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | adi,ltc2992.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| H A D | aspeed-pwm-tacho.txt | 7 one/two Fan tach inputs.
9 Required properties for pwm-tacho node:
10 - #address-cells : should be 1.
12 - #size-cells : should be 1.
14 - #cooling-cells: should be 2.
16 - reg : address and length of the register set for the device.
18 - pinctr
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| /freebsd/share/man/man4/ |
| H A D | ng_l2cap.4 | 1 .\" Copyright (c) 2001-2002 Maksim Yevmenkin <m_evmenkin@yahoo.com>
45 L2CAP provides connection-oriented and connectionless data services to upper
52 .Bl -enum -offset indent
54 The ACL link between two units is set up.
58 No more than one ACL link exists between any two devices.
60 The Baseband always provides the impression of full-duplex communication
62 This does not imply that all L2CAP communications are bi-directional.
66 L2CAP provides a reliable channel using the mechanisms available at the
78 Each channel is bound to a single protocol in a many-to-one fashion.
80 channels can be bound to the same protocol, but a channel cannot be bound to
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|
| /freebsd/share/man/man9/ |
| H A D | ieee80211_radiotap.9 | 60 layer used by 802.11 drivers includes support for a device-independent
68 Radiotap was designed to balance the desire for a hardware-independent,
78 defines two packed structures that it shares with
93 With radiotap setup, drivers just need to fill in per-packet
105 .Bd -literal -offset indent
115 .Bd -literal -offset indent
129 .Bl -tag -width indent
131 This field contains the unsigned 64-bit value, in microseconds,
138 This field contains a single unsigned 8-bit value, containing one or
140 .Bl -tag -width indent
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
4 registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
5 specific DMA request source can only be multiplexed by any channel of certain
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
17 The 2nd and the 3rd regions are programmable channel multiplexing
19 - interrupts : A list of interrupt-specifiers, one for each entry in
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|
| H A D | owl-dma.txt | 6 - compatible: Should be "actions,s900-dma".
7 - reg: Should contain DMA registers location and length.
8 - interrupts: Should contain 4 interrupts shared by all channel.
9 - #dma-cells: Must be <1>. Used to represent the number of integer
11 - dma-channels: Physical channels supported.
12 - dma-requests: Number of DMA request signals supported by the controller.
14 - clocks: Phandle and Specifier of the clock feeding the DMA controller.
19 dma: dma-controller@e0260000 {
20 compatible = "actions,s900-dma";
26 #dma-cells = <1>;
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|
| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | arm,scmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
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| /freebsd/contrib/wpa/wpa_supplicant/ |
| H A D | op_classes.c | 6 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 for (i = 0; i < mode->num_channels; i++) { in allow_channel()
30 chan_is_6ghz = is_6ghz_freq(mode->channels[i].freq); in allow_channel()
31 if (is_6ghz == chan_is_6ghz && mode->channels[i].chan == chan) in allow_channel()
35 if (i == mode->num_channels || in allow_channel()
36 (mode->channels[i].flag & HOSTAPD_CHAN_DISABLED)) in allow_channel()
40 *flags = mode->channels[i].flag; in allow_channel()
42 if (mode->channels[i].flag & HOSTAPD_CHAN_NO_IR) in allow_channel()
49 static int get_center_80mhz(struct hostapd_hw_modes *mode, u8 channel, in get_center_80mhz() argument
54 if (mode->mode != HOSTAPD_MODE_IEEE80211A) in get_center_80mhz()
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| /freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/ |
| H A D | resistive-adc-touch.txt | 5 - compatible: must be "resistive-adc-touch"
9 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml
12 - iio-channels: must have at least two channels connected to an ADC device.
16 - iio-channel-names: must have all the channels' names. Mandatory channels
20 - iio-channels: The third channel named "pressure" is optional and can be
22 If this channel is missing, pressure will be ignored and the touchscreen
24 - iio-channel-names: optional channel named "pressure".
29 compatible = "resistive-adc-touch";
30 touchscreen-min-pressure = <50000>;
31 io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
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|