Lines Matching +full:two +full:- +full:channel
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
20 | |-----SD0------->|D0 |
21 | |-----SD1------->|D1 |
22 +---------------------+ +---------------------+
24 As per datasheet, each DRIF channel (drifn) is made up of two internal
25 channels (drifn0 & drifn1). These two internal channels share the common
26 CLK & SYNC. Each internal channel has its own dedicated resources like
30 The device tree model represents each internal channel as a separate node.
33 the documentation, unless explicitly stated, the word channel implies an
34 internal channel.
38 two, one of them needs to act as a primary device that accepts common
39 properties of both the internal channels. This channel is identified by a
40 property called "renesas,primary-bond".
44 the zeroth channel is selected as primary-bond. This channels accepts
47 "renesas,bonding" or "renesas,primary-bond" will have no effect. That
48 enabled channel can act alone as any other independent device.
53 - enum:
54 - renesas,r8a7795-drif # R-Car H3
55 - renesas,r8a7796-drif # R-Car M3-W
56 - renesas,r8a77965-drif # R-Car M3-N
57 - renesas,r8a77990-drif # R-Car E3
58 - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
69 clock-names:
79 dma-names:
82 - const: rx
83 - const: rx
88 The phandle to the other internal channel of DRIF
90 power-domains:
93 renesas,primary-bond:
96 Indicates that the channel acts as primary among the bonded channels.
99 $ref: /schemas/graph.yaml#/$defs/port-base
107 $ref: /schemas/graph.yaml#/$defs/endpoint-base
111 sync-active:
120 - compatible
121 - reg
122 - interrupts
123 - clocks
124 - clock-names
125 - resets
126 - dmas
127 - dma-names
128 - renesas,bonding
129 - power-domains
132 - if:
134 - renesas,primary-bond
137 - pinctrl-0
138 - pinctrl-names
139 - port
141 - if:
143 - port
146 - pinctrl-0
147 - pinctrl-names
150 pinctrl-0: false
151 pinctrl-names: false
158 # When interfacing with a third party tuner device with two data pins as shown
161 # +---------------------+ +---------------------+
162 # | |-----SCK------->|CLK |
163 # | Master |-----SS-------->|SYNC DRIFn (slave) |
164 # | |-----SD0------->|D0 |
165 # | |-----SD1------->|D1 |
166 # +---------------------+ +---------------------+
167 - |
168 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
169 #include <dt-bindings/interrupt-controller/arm-gic.h>
170 #include <dt-bindings/power/r8a7795-sysc.h>
173 #address-cells = <2>;
174 #size-cells = <2>;
177 compatible = "renesas,r8a7795-drif",
178 "renesas,rcar-gen3-drif";
182 clock-names = "fck";
184 dma-names = "rx", "rx";
185 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
188 renesas,primary-bond;
189 pinctrl-0 = <&drif0_pins>;
190 pinctrl-names = "default";
193 remote-endpoint = <&tuner_ep>;
199 compatible = "renesas,r8a7795-drif",
200 "renesas,rcar-gen3-drif";
204 clock-names = "fck";
206 dma-names = "rx", "rx";
207 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
213 # Example with internal channel 1 alone enabled.
218 # +---------------------+ +---------------------+
219 # | |-----SCK------->|CLK |
220 # | Master |-----SS-------->|SYNC DRIFn (slave) |
222 # | |-----SD-------->|D1 |
223 # +---------------------+ +---------------------+
224 - |
225 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
226 #include <dt-bindings/interrupt-controller/arm-gic.h>
227 #include <dt-bindings/power/r8a7795-sysc.h>
230 #address-cells = <2>;
231 #size-cells = <2>;
234 compatible = "renesas,r8a7795-drif",
235 "renesas,rcar-gen3-drif";
239 clock-names = "fck";
241 dma-names = "rx", "rx";
242 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
248 compatible = "renesas,r8a7795-drif",
249 "renesas,rcar-gen3-drif";
253 clock-names = "fck";
255 dma-names = "rx", "rx";
256 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
259 pinctrl-0 = <&drif1_pins>;
260 pinctrl-names = "default";
263 remote-endpoint = <&tuner_ep1>;
264 sync-active = <0>;