Home
last modified time | relevance | path

Searched full:timing (Results 1 – 25 of 814) sorted by relevance

12345678910>>...33

/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-am654.yaml62 description: Output tap delay for SD/MMC legacy timing
68 description: Output tap delay for MMC high speed timing
74 description: Output tap delay for SD high speed timing
80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
98 description: Output tap delay for SD UHS SDR104 timing
104 description: Output tap delay for SD UHS DDR50 timing
110 description: Output tap delay for eMMC DDR52 timing
116 description: Output tap delay for eMMC HS200 timing
[all …]
H A Dsdhci-sprd.txt33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
H A Dsamsung,exynos-dw-mshc.yaml58 samsung,dw-mshc-ddr-timing:
70 See also samsung,dw-mshc-hs400-timing property.
72 samsung,dw-mshc-hs400-timing:
84 Valid values for SDR and DDR CIU clock timing::
90 If missing, values from samsung,dw-mshc-ddr-timing property are used.
92 samsung,dw-mshc-sdr-timing:
104 See also samsung,dw-mshc-hs400-timing property.
118 - samsung,dw-mshc-ddr-timing
119 - samsung,dw-mshc-sdr-timing
155 samsung,dw-mshc-sdr-timing
[all...]
H A Dexynos-dw-mshc.txt32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
37 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
41 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
44 Notes for the sdr-timing and ddr-timing values:
50 Valid values for SDR and DDR CIU clock timing for Exynos5250:
89 samsung,dw-mshc-sdr-timing = <2 3>;
90 samsung,dw-mshc-ddr-timing = <1 2>;
91 samsung,dw-mshc-hs400-timing = <0 2>;
H A Dcdns,sdhci.yaml40 description: Value of the delay in the input path for SD high-speed timing
46 description: Value of the delay in the input path for legacy timing
52 description: Value of the delay in the input path for SD UHS SDR12 timing
58 description: Value of the delay in the input path for SD UHS SDR25 timing
64 description: Value of the delay in the input path for SD UHS SDR50 timing
70 description: Value of the delay in the input path for SD UHS DDR50 timing
76 description: Value of the delay in the input path for MMC high-speed timing
82 description: Value of the delay in the input path for eMMC high-speed DDR timing
/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
H A Dxlnx,v-tpg.txt26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
/freebsd/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/freebsd/sys/dev/mmc/
H A Dmmc.c190 static bool mmc_host_timing(device_t dev, enum mmc_bus_timing timing);
212 enum mmc_bus_timing timing);
216 enum mmc_bus_timing timing);
218 enum mmc_bus_timing timing);
225 enum mmc_bus_timing timing);
226 static const char *mmc_timing_to_string(enum mmc_bus_timing timing);
321 enum mmc_bus_timing timing; in mmc_acquire_bus() local
349 timing = mmcbr_get_timing(busdev); in mmc_acquire_bus()
362 if (timing >= bus_timing_mmc_ddr52 && in mmc_acquire_bus()
368 "setting bus width to %d bits %s timing\ in mmc_acquire_bus()
742 mmc_set_card_bus_width(struct mmc_softc * sc,struct mmc_ivars * ivar,enum mmc_bus_timing timing) mmc_set_card_bus_width() argument
825 enum mmc_bus_timing timing; mmc_set_power_class() local
897 mmc_set_timing(struct mmc_softc * sc,struct mmc_ivars * ivar,enum mmc_bus_timing timing) mmc_set_timing() argument
956 mmc_set_vccq(struct mmc_softc * sc,struct mmc_ivars * ivar,enum mmc_bus_timing timing) mmc_set_vccq() argument
1454 mmc_timing_to_dtr(struct mmc_ivars * ivar,enum mmc_bus_timing timing) mmc_timing_to_dtr() argument
1483 mmc_timing_to_string(enum mmc_bus_timing timing) mmc_timing_to_string() argument
1510 mmc_host_timing(device_t dev,enum mmc_bus_timing timing) mmc_host_timing() argument
1561 enum mmc_bus_timing timing; mmc_log_card() local
2116 enum mmc_bus_timing max_timing, timing; mmc_calculate_clock() local
2362 enum mmc_bus_timing timing; mmc_retune() local
[all...]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dahci-ceva.txt8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
25 - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
33 - ceva,p1-retry-params: Retry interval timing value for port 1.
H A Dceva,ahci-1v84.yaml44 OOB timing value for COMINIT parameter for port 0.
56 OOB timing value for COMWAKE parameter for port 0.
68 Burst timing value for COM parameter for port 0.
80 Retry interval timing value for port 0.
90 OOB timing value for COMINIT parameter for port 1.
102 OOB timing value for COMWAKE parameter for port 1.
114 Burst timing value for COM parameter for port 1.
126 Retry interval timing value for port 1.
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt29 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set
32 Each "emc-timings" node should contain a "timing" subnode for every supported
35 Required properties for "timing" nodes :
36 - clock-frequency : Should contain the memory clock rate to which this timing
39 parent of the EMC clock should be running at this timing.
44 timing.
93 timing-12750000 {
99 timing-20400000 {
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf300t.dts150 timing-25500000 {
160 timing-51000000 {
170 timing-102000000 {
180 timing-204000000 {
190 timing-333500000 {
200 timing-667000000 {
215 timing-25500000 {
225 timing-51000000 {
235 timing-102000000 {
245 timing-204000000 {
[all …]
H A Dtegra124-apalis-emc.dtsi14 timing-12750000 {
21 timing-20400000 {
28 timing-40800000 {
35 timing-68000000 {
42 timing-102000000 {
49 timing-204000000 {
56 timing-300000000 {
63 timing-396000000 {
70 timing-528000000 {
77 timing-600000000 {
[all …]
H A Dtegra30-asus-tf300tg.dts224 timing-25500000 {
234 timing-51000000 {
244 timing-102000000 {
254 timing-204000000 {
264 timing-333500000 {
274 timing-667000000 {
289 timing-25500000 {
299 timing-51000000 {
309 timing-102000000 {
319 timing-204000000 {
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi10 timing-12750000 {
17 timing-20400000 {
24 timing-40800000 {
31 timing-68000000 {
38 timing-102000000 {
45 timing-204000000 {
52 timing-300000000 {
59 timing-396000000 {
66 timing-528000000 {
73 timing-600000000 {
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi10 timing-12750000 {
17 timing-20400000 {
24 timing-40800000 {
31 timing-68000000 {
38 timing-102000000 {
45 timing-204000000 {
52 timing-300000000 {
59 timing-396000000 {
68 timing-600000000 {
75 timing-792000000 {
[all …]
H A Dtegra30-asus-tf700t.dts145 timing-25500000 {
155 timing-51000000 {
165 timing-102000000 {
175 timing-204000000 {
185 timing-400000000 {
195 timing-800000000 {
210 timing-25500000 {
220 timing-51000000 {
230 timing-102000000 {
240 timing
[all...]
H A Dtegra30-asus-tf201.dts116 timing-25500000 {
126 timing-51000000 {
136 timing-102000000 {
146 timing-204000000 {
156 timing-400000000 {
171 timing-25500000 {
181 timing-51000000 {
191 timing-102000000 {
201 timing-204000000 {
211 timing-500000000 {
[all …]
/freebsd/sys/dev/ow/
H A Dowll_if.m44 # Maxim datasheets also describe how to use UARTs to generate timing,
47 # Chapter 4 has all the electrical timing diagrams that make up the link
94 struct ow_timing *timing; /* timing values */
112 struct ow_timing *timing; /* timing values */
130 struct ow_timing *timing; /* timing values */
154 struct ow_timing *timing; /* timing values */
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-timing.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
7 title: panel timing
14 There are different ways of describing the timing data of a panel. The
46 This matches the timing diagrams often found in data sheets.
56 Timing can be specified either as a typical value or as a tuple
73 description: Horizontal front porch panel timing
85 description: Horizontal back porch timing
97 description: Horizontal sync length panel timing
109 description: Vertical front porch panel timing
121 description: Vertical back porch panel timing
[all …]
H A Ddisplay-timings.yaml18 and to specify the timing that is native for the display.
27 The default display timing is the one specified as native-mode.
32 "^timing":
34 $ref: panel-timing.yaml#
42 * Example that specifies panel timing using minimum, typical,
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dtdls.h23 * struct iwl_tdls_channel_switch_timing - Switch timing in TDLS channel-switch
30 * @switch_time: switch time the peer sent in its channel switch timing IE
31 * @switch_timeout: switch timeout the peer sent in its channel switch timing IE
47 * @switch_time_offset: offset to the channel switch timing IE in the template
60 * @timing: timing related data for command
64 struct iwl_tdls_channel_switch_timing timing; member
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dimx-weim.txt56 Timing property for child nodes. It is mandatory, not optional.
58 - fsl,weim-cs-timing: The timing array, contains timing values for the
88 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
95 In this case, both chip select 0 and 1 will be configured with the same timing
114 fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
/freebsd/sys/dev/drm2/
H A Ddrm_edid.c60 /* Detail timing is in cm not mm */
62 /* Detailed timing descriptors have bogus size values, so just take the
578 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
704 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
733 * @t: standard timing params
734 * @timing_level: standard timing level
736 * Take the standard timing params (in this case width, aspect, and refresh)
890 * drm_mode_detailed - create a new mode from an EDID detailed timing section
893 * @timing: EDID detailed timing info
896 * An EDID detailed timing block contains enough info for us to create and
[all …]

12345678910>>...33