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/linux/drivers/hwtracing/coresight/
H A Dcoresight-tmc.h56 * TMC AXICTL format for SoC-400
63 * TMC AXICTL format for SoC-600, as above except:
123 /* TMC ETR Capability bit definitions */
129 * retained when TMC leaves Disabled state, allowing us to continue
137 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
141 /* TMC metadata region for ETR and ETF configurations */
162 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
176 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}
212 * struct tmc_drvdata - specifics associated to an TMC component
213 * @atclk: optional clock for the core parts of the TMC.
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H A Dcoresight-tmc-etf.c13 #include "coresight-tmc.h"
30 "Failed to enable: TMC not ready\n"); in __tmc_etb_enable_hw()
93 * read before the TMC is disabled. in __tmc_etb_disable_hw()
118 "Failed to enable : TMC is not ready\n"); in __tmc_etf_enable_hw()
329 dev_dbg(&csdev->dev, "TMC-ETB/ETF enabled\n"); in tmc_enable_etf_sink()
360 dev_dbg(&csdev->dev, "TMC-ETB/ETF disabled\n"); in tmc_disable_etf_sink()
391 dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); in tmc_enable_etf_link()
418 dev_dbg(&csdev->dev, "TMC-ETF disabled\n"); in tmc_disable_etf_link()
522 * The TMC RAM buffer may be bigger than the space available in the in tmc_update_etf_buffer()
738 /* Disable the TMC if need be */ in tmc_read_prepare_etb()
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H A Dcoresight-tmc-etr.c20 #include "coresight-tmc.h"
63 * The TMC ETR SG has a page size of 4K. The SG table contains pointers
110 * @hwaddr: hwaddress used by the TMC, which is the base
123 * Each TMC page can map (ETR_SG_PTRS_PER_PAGE - 1) buffer pointers,
316 * tmc_alloc_sg_table: Allocate and setup dma pages for the TMC SG table
317 * and data buffers. TMC writes to the data buffers and reads from the SG
561 * tmc_init_etr_sg_table: Allocate a TMC ETR SG table, data buffer of @size and
564 * @dev - Device pointer for the TMC
591 /* TMC should use table base address for DBA */ in tmc_init_etr_sg_table()
847 * TMC ETR could be connected to a CATU device, which can provide address
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H A Dcoresight-ctcu-core.c28 * The TMC Coresight Control Unit utilizes four ATID registers to control the data
29 * filter function based on the trace ID for each TMC ETR sink. The length of each
89 * @port_num: port number connected to TMC ETR sink.
313 MODULE_DESCRIPTION("CoreSight TMC Control Unit driver");
H A Dcoresight-catu.c21 #include "coresight-tmc.h"
555 /* Default to the 40bits as supported by TMC-ETR */ in __catu_probe()
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-usb-usbtmc6 These files show the various USB TMC capabilities as described
8 can be found in the USB TMC documents from the USB-IF entitled
20 These files show the various USB TMC capabilities as described
22 can be found in the USB TMC documents from the USB-IF entitled
/linux/drivers/net/wan/
H A Dhd64572.c362 unsigned int tmc, br = 10, brv = 1024; in sca_set_port() local
370 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ in sca_set_port()
371 tmc = CLOCK_BASE / brv / port->settings.clock_rate; in sca_set_port()
372 } while (br > 1 && tmc <= 128); in sca_set_port()
374 if (tmc < 1) { in sca_set_port()
375 tmc = 1; in sca_set_port()
376 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ in sca_set_port()
378 } else if (tmc > 255) { in sca_set_port()
379 tmc = 256; /* tmc=0 means 256 - low baud rates */ in sca_set_port()
382 port->settings.clock_rate = CLOCK_BASE / brv / tmc; in sca_set_port()
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H A Dhd64570.c406 unsigned int tmc, br = 10, brv = 1024; in sca_set_port() local
414 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ in sca_set_port()
415 tmc = CLOCK_BASE / brv / port->settings.clock_rate; in sca_set_port()
416 } while (br > 1 && tmc <= 128); in sca_set_port()
418 if (tmc < 1) { in sca_set_port()
419 tmc = 1; in sca_set_port()
420 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ in sca_set_port()
422 } else if (tmc > 255) { in sca_set_port()
423 tmc = 256; /* tmc=0 means 256 - low baud rates */ in sca_set_port()
426 port->settings.clock_rate = CLOCK_BASE / brv / tmc; in sca_set_port()
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H A Dhd64570.h67 #define TMC 0x15 /* Time Constant */ macro
/linux/drivers/scsi/
H A Dfdomain_isa.c35 /* This driver works *ONLY* for Future Domain cards using the TMC-1800,
36 * TMC-18C50, or TMC-18C30 chip. This includes models TMC-1650, 1660, 1670,
41 * work with this driver (these TMC-8xx and TMC-9xx boards may work with the
74 { "FUTURE DOMAIN TMC-18XX (C) 1993 V3.203/12/93", 5, 44, 7, 0 },
218 MODULE_DESCRIPTION("Future Domain TMC-16x0 ISA SCSI driver");
H A Dfdomain_pci.c67 MODULE_DESCRIPTION("Future Domain TMC-3260 PCI SCSI driver");
H A DKconfig661 tristate "Future Domain TMC-3260/AHA-2920A PCI SCSI support"
665 This is support for Future Domain's PCI SCSI host adapters (TMC-3260)
684 (TMC-1660/1680, TMC-1650/1670, TMC-1610M/MER/MEX) and other adapters
/linux/Documentation/admin-guide/media/
H A Dci.rst35 eg: $ szap -c channels.conf -r "TMC" -x
39 eg: TMC:11996:h:0:27500:278:512:650:321
47 eg: $ ca_zap channels.conf "TMC"
H A Dsi470x.rst36 - Si4706: Enhanced FM RDS/TMC radio receiver, no external antenna required, RDS
85 There is currently no project for making TMC sentences human readable.
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi136 compatible = "arm,coresight-tmc", "arm,primecell";
282 compatible = "arm,coresight-tmc", "arm,primecell";
374 compatible = "arm,coresight-tmc", "arm,primecell";
433 compatible = "arm,coresight-tmc", "arm,primecell";
H A Dhi6220-coresight.dtsi39 compatible = "arm,coresight-tmc", "arm,primecell";
100 compatible = "arm,coresight-tmc", "arm,primecell";
369 /* CTI 0 - TMC and TPIU connections */
/linux/include/uapi/linux/usb/
H A Dtmc.h22 /* USB TMC status values */
30 /* USB TMC requests values */
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi275 compatible = "arm,coresight-tmc", "arm,primecell";
403 compatible = "arm,coresight-tmc", "arm,primecell";
428 compatible = "arm,coresight-tmc", "arm,primecell";
H A Dums512.dtsi486 compatible = "arm,coresight-tmc", "arm,primecell";
553 compatible = "arm,coresight-tmc", "arm,primecell";
579 compatible = "arm,coresight-tmc", "arm,primecell";
H A Dsc9836.dtsi48 compatible = "arm,coresight-tmc", "arm,primecell";
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-catu.yaml24 AXI master and system memory. The CATU is normally used along with the TMC to
/linux/arch/arm64/boot/dts/arm/
H A Djuno-cs-r1r2.dtsi27 compatible = "arm,coresight-tmc", "arm,primecell";
H A Djuno-base.dtsi121 compatible = "arm,coresight-tmc", "arm,primecell";
198 compatible = "arm,coresight-tmc", "arm,primecell";
/linux/drivers/eisa/
H A Deisa.ids668 ICU0580 "TMC-850M/TMC-850RL SCSI Controller"
669 ICU0590 "Future Domain TMC-880/TMC-881 SCSI Controller"
670 ICU05A0 "Future Domain TMC-1650/1660/1670/1680 SCSI Controller V5"
671 ICU05B0 "Future Domain TMC-1650/1660/1670/1680 SCSI Controller V4"
/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h624 * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
640 /* Taud = 32*ASD*Tmc */
645 /* Taud = 32*Floor (Div/32)*Tmc */
649 /* Taud = 32*Ceil (Div/32)*Tmc */
653 /* Ttcm = 32*TSD*Tmc */
658 /* Ttcm = 32*Floor (Div/32)*Tmc */
662 /* Ttcm = 32*Ceil (Div/32)*Tmc */

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