| /linux/Documentation/devicetree/bindings/hwlock/ |
| H A D | qcom-hwspinlock.yaml | 21 - qcom,tcsr-mutex
24 - qcom,apq8084-tcsr-mutex
25 - qcom,ipq6018-tcsr-mutex
26 - qcom,msm8226-tcsr-mutex
27 - qcom,msm8994-tcsr-mutex
28 - const: qcom,tcsr-mutex
31 - qcom,msm8974-tcsr-mutex
32 - const: qcom,tcsr-mutex
51 compatible = "qcom,tcsr-mutex";
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| /linux/include/clocksource/ |
| H A D | timer-xilinx.h | 51 * @tcsr: The value of the TCSR register for this counter
59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
66 * @tcsr: The value of TCSR for this counter
71 u32 tlr, u32 tcsr);
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| /linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,gsbi.yaml | 57 syscon-tcsr:
60 Phandle of TCSR syscon node.Required if child uses dma.
106 syscon-tcsr = <&tcsr>;
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| /linux/drivers/hwspinlock/ |
| H A D | qcom_hwspinlock.c | 141 { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
142 { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
143 { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
144 { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
145 { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qusb2.c | 304 /* offset to PHY_CLK_SCHEME register in TCSR map */
467 * @tcsr: TCSR syscon register map in qusb2_setbits()
487 struct regmap *tcsr;
845 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
856 if (qphy->tcsr) { in qusb2_phy_init()
857 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1064 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1065 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1066 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
438 struct regmap *tcsr; global() member
[all...] |
| /linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-ipq8064.dtsi | 760 syscon-tcsr = <&tcsr>;
799 syscon-tcsr = <&tcsr>;
836 syscon-tcsr = <&tcsr>;
872 syscon-tcsr = <&tcsr>;
915 syscon-tcsr = <&tcsr>;
974 syscon-tcsr = <&tcsr>;
1013 tcsr: syscon@1a400000 { label
1014 compatible = "qcom,tcsr-ipq8064", "syscon";
|
| H A D | qcom-apq8064.dtsi | 424 syscon-tcsr = <&tcsr>;
463 syscon-tcsr = <&tcsr>;
624 syscon-tcsr = <&tcsr>;
989 tcsr: syscon@1a400000 { label
990 compatible = "qcom,tcsr-apq8064", "syscon";
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| /linux/drivers/clk/qcom/ |
| H A D | tcsrcc-sm8550.c | 14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
170 { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc },
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| H A D | tcsrcc-x1e80100.c | 13 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
254 { .compatible = "qcom,x1e80100-tcsr" },
284 MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver");
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| H A D | tcsrcc-sm8650.c | 14 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
151 { .compatible = "qcom,sm8650-tcsr" },
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie-ep.yaml | 54 description: Reference to a syscon representing TCSR followed by the two
60 - description: Syscon to TCSR system registers
266 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
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| /linux/drivers/pwm/ |
| H A D | pwm-xilinx.c | 34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, in xilinx_timer_tlr_cycles() argument
39 if (tcsr & TCSR_UDT) in xilinx_timer_tlr_cycles()
45 u32 tlr, u32 tcsr) in xilinx_timer_get_period() argument
49 if (tcsr & TCSR_UDT) in xilinx_timer_get_period()
|
| /linux/drivers/pmdomain/qcom/ |
| H A D | cpr.c | 237 struct regmap *tcsr; member
393 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f, in cpr_set_acc() argument
401 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
404 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
414 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
415 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
426 if (drv->tcsr && dir == UP) in cpr_post_voltage()
427 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
1517 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1522 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
[all …]
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| /linux/Documentation/arch/mips/ |
| H A D | ingenic-tcu.rst | 19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
|
| /linux/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2_tai.c | 242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
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| /linux/drivers/clk/ingenic/ |
| H A D | tcu.c | 130 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_get_parent()
146 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_parent()
163 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_recalc_rate()
212 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_rate()
|
| /linux/include/dt-bindings/clock/ |
| H A D | qcom,sc8280xp-lpasscc.h | 14 /* LPASS TCSR */
|
| H A D | qcom,sm8550-tcsr.h | 10 /* TCSR CC clocks */
|
| H A D | qcom,sm8650-tcsr.h | 10 /* TCSR CC clocks */
|
| H A D | qcom,x1e80100-tcsr.h | 9 /* TCSR CC clocks */
|
| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | ipq6018.dtsi | 99 qcom,dload-mode = <&tcsr 0x6100>;
409 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
414 tcsr: syscon@1937000 { label
415 compatible = "qcom,tcsr-ipq6018", "syscon";
847 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,msm8916-mss-pil.yaml | 116 - description: phandle to TCSR syscon region
265 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
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| /linux/drivers/rtc/ |
| H A D | rtc-rs5c348.c | 101 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_set_time()
133 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_read_time()
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| /linux/Documentation/translations/zh_CN/arch/mips/ |
| H A D | ingenic-tcu.rst | 25 - 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟
|
| /linux/Documentation/translations/zh_TW/arch/mips/ |
| H A D | ingenic-tcu.rst | 25 - 每個TCU通道都有自己的時鐘源，可以通過 TCSR 寄存器設置通道的父級時鐘
|