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/linux/Documentation/devicetree/bindings/mfd/
H A Dqcom,tcsr.yaml4 $id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
20 - qcom,msm8976-tcsr
21 - qcom,msm8998-tcsr
22 - qcom,qcm2290-tcsr
23 - qcom,qcs404-tcsr
24 - qcom,qcs615-tcsr
25 - qcom,qcs8300-tcsr
26 - qcom,sa8255p-tcsr
27 - qcom,sa8775p-tcsr
28 - qcom,sc7180-tcsr
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8550-tcsr.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
14 Qualcomm TCSR clock control module provides the clocks, resets and
18 - include/dt-bindings/clock/qcom,glymur-tcsr.h
19 - include/dt-bindings/clock/qcom,sm8550-tcsr.h
20 - include/dt-bindings/clock/qcom,sm8650-tcsr.h
21 - include/dt-bindings/clock/qcom,sm8750-tcsr.h
27 - qcom,glymur-tcsr
28 - qcom,kaanapali-tcsr
29 - qcom,milos-tcsr
[all …]
/linux/Documentation/devicetree/bindings/hwlock/
H A Dqcom-hwspinlock.yaml21 - qcom,tcsr-mutex
24 - qcom,apq8084-tcsr-mutex
25 - qcom,ipq6018-tcsr-mutex
26 - qcom,msm8226-tcsr-mutex
27 - qcom,msm8994-tcsr-mutex
28 - const: qcom,tcsr-mutex
31 - qcom,msm8974-tcsr-mutex
32 - const: qcom,tcsr-mutex
51 compatible = "qcom,tcsr-mutex";
/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c114 struct regmap *tcsr; member
118 { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
119 { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
120 { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
121 { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
145 /* get the tcsr node and setup the config and regmap */ in gsbi_probe()
146 gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); in gsbi_probe()
148 if (!IS_ERR(gsbi->tcsr)) { in gsbi_probe()
149 tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0); in gsbi_probe()
155 dev_warn(&pdev->dev, "no matching TCSR\n"); in gsbi_probe()
[all …]
/linux/include/clocksource/
H A Dtimer-xilinx.h51 * @tcsr: The value of the TCSR register for this counter
59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
66 * @tcsr: The value of TCSR for this counter
71 u32 tlr, u32 tcsr);
/linux/drivers/hwspinlock/
H A Dqcom_hwspinlock.c141 { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
142 { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
143 { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
144 { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
145 { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c289 /* offset to PHY_CLK_SCHEME register in TCSR map */
442 * @tcsr: TCSR syscon register map
462 struct regmap *tcsr; member
820 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
831 if (qphy->tcsr) { in qusb2_phy_init()
832 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1039 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1040 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1041 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1042 dev_dbg(dev, "failed to lookup TCSR regmap\n"); in qusb2_phy_probe()
[all …]
/linux/drivers/clk/qcom/
H A Dtcsrcc-sm8550.c14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
170 { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc },
H A Dtcsrcc-x1e80100.c13 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
258 { .compatible = "qcom,x1e80100-tcsr" },
288 MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver");
H A Dtcsrcc-glymur.c13 #include <dt-bindings/clock/qcom,glymur-tcsr.h>
282 { .compatible = "qcom,glymur-tcsr" },
/linux/drivers/pmdomain/qcom/
H A Dcpr.c237 struct regmap *tcsr; member
393 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f, in cpr_set_acc() argument
401 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
404 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
414 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
415 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
426 if (drv->tcsr && dir == UP) in cpr_post_voltage()
427 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
1517 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1522 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
[all …]
/linux/drivers/pwm/
H A Dpwm-xilinx.c34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, in xilinx_timer_tlr_cycles() argument
39 if (tcsr & TCSR_UDT) in xilinx_timer_tlr_cycles()
45 u32 tlr, u32 tcsr) in xilinx_timer_get_period() argument
49 if (tcsr & TCSR_UDT) in xilinx_timer_get_period()
/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml60 Phandler of TCSR node with two argument that indicate register
64 - description: phandle to TCSR node
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_tai.c242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
/linux/drivers/clk/ingenic/
H A Dtcu.c130 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_get_parent()
146 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_parent()
163 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_recalc_rate()
212 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_rate()
/linux/Documentation/devicetree/bindings/ufs/
H A Dqcom,sm8650-ufshc.yaml75 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
96 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
/linux/Documentation/devicetree/bindings/firmware/
H A Dqcom,scm.yaml123 - description: phandle to TCSR hardware block
125 description: TCSR hardware block
/linux/include/dt-bindings/clock/
H A Dqcom,sc8280xp-lpasscc.h14 /* LPASS TCSR */
H A Dqcom,sm8550-tcsr.h10 /* TCSR CC clocks */
H A Dqcom,sm8650-tcsr.h10 /* TCSR CC clocks */
H A Dqcom,x1e80100-tcsr.h9 /* TCSR CC clocks */
/linux/drivers/rtc/
H A Drtc-rs5c348.c101 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_set_time()
133 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_read_time()
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi317 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
389 compatible = "qcom,tcsr-mutex";
394 tcsr: syscon@1fcb000 { label
395 compatible = "qcom,sdx65-tcsr", "syscon";
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml97 - description: phandle of TCSR syscon
301 qcom,4ln-config-sel = <&tcsr 0xa044 0>;

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