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/linux/drivers/phy/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek 10GE SerDes XFI T-PHY driver"
22 Say 'Y' here to add support for MediaTek XFI T-PHY driver.
23 The driver provides access to the Ethernet SerDes T-PHY supporting
28 tristate "MediaTek T-PHY Driver"
34 Say 'Y' here to add support for MediaTek T-PHY driver,
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
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H A Dmediatek,mt7988-xfi-tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7988 XFI T-PHY
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
15 MediaTek's 10G-capabale MT7988 SoC.
20 const: mediatek,mt7988-xfi-tphy
27 - description: XFI PHY clock
[all …]
H A Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
11 - Julien Stephan <jstephan@baylibre.com>
12 - Andy Hsieh <andy.hsieh@mediatek.com>
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
23 - mediatek,mt8365-csi-rx
[all …]
/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
61 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) in u2_phy_w32() argument
63 writel(val, phy->base + reg); in u2_phy_w32()
66 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) in u2_phy_r32() argument
68 return readl(phy->base + reg); in u2_phy_r32()
71 static void ralink_usb_phy_init(struct ralink_usb_phy *phy) in ralink_usb_phy_init() argument
73 u2_phy_r32(phy, OFS_U2_PHY_AC2); in ralink_usb_phy_init()
74 u2_phy_r32(phy, OFS_U2_PHY_ACR0); in ralink_usb_phy_init()
[all …]
/linux/drivers/usb/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
32 tristate "Keystone USB PHY Driver"
36 Enable this to support Keystone USB phy. This driver provides
37 interface to interact with USB 2.0 and USB 3.0 PHY that is part
42 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
46 built-in with usb ip or which are autonomous and doesn't require any
47 phy programming such as ISP1x04 etc.
53 tristate "AM335x USB PHY Driver"
60 This driver provides PHY support for that phy which part for the
[all …]
/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
300 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) in ti_pipe3_get_dpll_params() argument
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
15 /* PHY Registers defined by IEEE */
18 #define PHY_ID1 0x02 /* Phy Id Register (word 1) */
19 #define PHY_ID2 0x03 /* Phy Id Register (word 2) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
28 #define PHY_PHYSP_CONTROL 0x10 /* PHY Specific Control Register */
[all …]
/linux/drivers/scsi/aic94xx/
H A Daic94xx_hwi.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* ---------- Initialization ---------- */
28 if (asd_ha->hw_prof.sas_addr[0]) in asd_get_user_sas_addr()
31 return sas_request_addr(asd_ha->sas_ha.shost, in asd_get_user_sas_addr()
32 asd_ha->hw_prof.sas_addr); in asd_get_user_sas_addr()
40 if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0) in asd_propagate_sas_addr()
42 /* Set a phy's address only if it has none. in asd_propagate_sas_addr()
44 ASD_DPRINTK("setting phy%d addr to %llx\n", i, in asd_propagate_sas_addr()
45 SAS_ADDR(asd_ha->hw_prof.sas_addr)); in asd_propagate_sas_addr()
46 memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr, in asd_propagate_sas_addr()
[all …]
H A Daic94xx_scb.c1 // SPDX-License-Identifier: GPL-2.0-only
19 /* ---------- EMPTY SCB ---------- */
36 static void get_lrate_mode(struct asd_phy *phy, u8 oob_mode) in get_lrate_mode() argument
38 struct sas_phy *sas_phy = phy->sas_phy.phy; in get_lrate_mode()
42 /* FIXME: sas transport class doesn't have this */ in get_lrate_mode()
43 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
44 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
47 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
48 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
51 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC/SD/SDIO core/phy configuration registers */
53 static int keembay_emmc_phy_power(struct phy *phy, bool on_off) in keembay_emmc_phy_power() argument
55 struct keembay_emmc_phy *priv = phy_get_drvdata(phy); in keembay_emmc_phy_power()
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
[all …]
/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
160 { PL_C_MIN, SLOW_C_MIN }, /* min t. to remain Connect State */
161 { PL_TL_MIN, SLOW_TL_MIN }, /* min t. to transmit a Line State */
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
32 reg-names:
[all …]
/linux/drivers/net/phy/
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Also contains generic PHY driver
29 #include <linux/phy.h>
33 #include <linux/pse-pd/pse.h>
44 #include "phylib-internal.h"
45 #include "phy-caps.h"
47 MODULE_DESCRIPTION("PHY librar
1515 phy_sfp_connect_phy(void * upstream,struct phy_device * phy) phy_sfp_connect_phy() argument
1537 phy_sfp_disconnect_phy(void * upstream,struct phy_device * phy) phy_sfp_disconnect_phy() argument
[all...]
H A Dphy_link_topology.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Infrastructure to handle all PHY devices connected to a given netdev,
10 #include <linux/phy.h>
20 return -ENOMEM; in netdev_alloc_phy_link_topology()
22 xa_init_flags(&topo->phys, XA_FLAGS_ALLOC1); in netdev_alloc_phy_link_topology()
23 topo->next_phy_index = 1; in netdev_alloc_phy_link_topology()
25 dev->link_topo = topo; in netdev_alloc_phy_link_topology()
31 struct phy_device *phy, in phy_link_topo_add_phy() argument
34 struct phy_link_topology *topo = dev->link_topo; in phy_link_topo_add_phy()
43 topo = dev->link_topo; in phy_link_topo_add_phy()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dppa8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PPA8548 Device Tree Source (36-bit address map)
7 * MPC8548 CDS Device Tree Source (36-bit address map)
11 /include/ "mpc8548si-pre.dtsi"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&mpic>;
35 /* ppa8548 board doesn't support PCI */
40 /* ppa8548 board doesn't support PCI */
45 /* ppa8548 board doesn't support PCI */
[all …]
H A Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
[all …]
H A Dp1020mbg-pc.dtsi2 * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
66 label = "NOR Vitesse-7385 Firmware";
67 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
/linux/Documentation/networking/
H A Dphy-link-topology.rst1 .. SPDX-License-Identifier: GPL-2.0
5 PHY link topology
11 The PHY link topology representation in the networking stack aims at representing
19 +-----------------------+ +----------+ +--------------+
21 | MAC | ------ | PHY | ---- | Port | ---... to LP
22 +-----------------------+ +----------+ +--------------+
25 Commands that needs to configure the PHY will go through the net_device.phydev
26 field to reach the PHY and perform the relevant configuration.
37 +-----+ SGMII +------------+
38 | MAC | ------- | SFP Module |
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dtx.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
11 if (!txq->sta) in mt76_txq_get_qid()
14 return txq->ac; in mt76_txq_get_qid()
20 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in mt76_tx_check_agg_ssn()
25 if (!sta || !ieee80211_is_data_qos(hdr->frame_control) || in mt76_tx_check_agg_ssn()
26 !ieee80211_is_data_present(hdr->frame_contro in mt76_tx_check_agg_ssn()
259 struct mt76_phy *phy = hw->priv; __mt76_tx_complete_skb() local
298 __mt76_tx_queue_skb(struct mt76_phy * phy,int qid,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_sta * sta,bool * stop) __mt76_tx_queue_skb() argument
331 mt76_tx(struct mt76_phy * phy,struct ieee80211_sta * sta,struct mt76_wcid * wcid,struct sk_buff * skb) mt76_tx() argument
373 mt76_txq_dequeue(struct mt76_phy * phy,struct mt76_txq * mtxq) mt76_txq_dequeue() argument
390 mt76_queue_ps_skb(struct mt76_phy * phy,struct ieee80211_sta * sta,struct sk_buff * skb,bool last) mt76_queue_ps_skb() argument
411 struct mt76_phy *phy = hw->priv; mt76_release_buffered_frames() local
458 mt76_txq_send_burst(struct mt76_phy * phy,struct mt76_queue * q,struct mt76_txq * mtxq,struct mt76_wcid * wcid) mt76_txq_send_burst() argument
524 mt76_txq_schedule_list(struct mt76_phy * phy,enum mt76_txq_id qid) mt76_txq_schedule_list() argument
580 mt76_txq_schedule(struct mt76_phy * phy,enum mt76_txq_id qid) mt76_txq_schedule() argument
602 mt76_txq_schedule_pending_wcid(struct mt76_phy * phy,struct mt76_wcid * wcid,struct sk_buff_head * head) mt76_txq_schedule_pending_wcid() argument
647 mt76_txq_schedule_pending(struct mt76_phy * phy) mt76_txq_schedule_pending() argument
684 mt76_txq_schedule_all(struct mt76_phy * phy) mt76_txq_schedule_all() argument
701 struct mt76_phy *phy; mt76_tx_worker_run() local
732 mt76_stop_tx_queues(struct mt76_phy * phy,struct ieee80211_sta * sta,bool send_bar) mt76_stop_tx_queues() argument
757 struct mt76_phy *phy = hw->priv; mt76_wake_tx_queue() local
820 struct mt76_phy *phy = &dev->phy; __mt76_set_tx_blocked() local
870 mt76_rx_token_consume(struct mt76_dev * dev,void * ptr,struct mt76_txwi_cache * t,dma_addr_t phys) mt76_rx_token_consume() argument
919 struct mt76_txwi_cache *t; mt76_rx_token_release() local
[all...]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
15 sets, clock and PHY.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
[all …]
/linux/drivers/scsi/
H A Dscsi_transport_sas.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2006 Dell Inc.
13 * introduces two additional intermediate objects: The SAS PHY
14 * as represented by struct sas_phy defines an "outgoing" PHY on
15 * a SAS HBA or Expander, and the SAS remote PHY represented by
16 * struct sas_rphy defines an "incoming" PHY on a SAS Expander or
18 * underlying hardware for a PHY and a remote PHY is the exactly
53 #define to_sas_host_attrs(host) ((struct sas_host_attrs *)(host)->shost_data)
102 return -EINVAL; \
151 { SAS_PHY_DISABLED, "Phy disabled" },
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmac.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
14 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2)
17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
31 .pulse_th = { 110, -10, -8
455 struct mt7996_phy *phy = &dev->phy; mt7996_mac_fill_rx() local
1041 struct mt76_txwi_cache *t; mt7996_tx_prepare_skb() local
1245 mt7996_txwi_free(struct mt7996_dev * dev,struct mt76_txwi_cache * t,struct ieee80211_link_sta * link_sta,struct mt76_wcid * wcid,struct list_head * free_list) mt7996_txwi_free() argument
1777 struct mt76_txwi_cache *t; mt7996_rx_token_put() local
1881 struct mt76_txwi_cache *t; mt7996_rro_rx_process() local
2031 mt7996_mac_cca_stats_reset(struct mt7996_phy * phy) mt7996_mac_cca_stats_reset() argument
2040 mt7996_mac_reset_counters(struct mt7996_phy * phy) mt7996_mac_reset_counters() argument
2060 mt7996_mac_set_coverage_class(struct mt7996_phy * phy) mt7996_mac_set_coverage_class() argument
2104 mt7996_phy_get_nf(struct mt7996_phy * phy,u8 band_idx) mt7996_phy_get_nf() argument
2126 struct mt7996_phy *phy = mphy->priv; mt7996_update_channel() local
2158 struct mt7996_phy *phy = priv; mt7996_update_vif_beacon() local
2184 mt7996_mac_update_beacons(struct mt7996_phy * phy) mt7996_mac_update_beacons() argument
2225 struct mt7996_phy *phy; mt7996_mac_restart() local
2410 struct mt7996_phy *phy; mt7996_mac_full_reset() local
2470 struct mt7996_phy *phy; mt7996_mac_reset_work() local
2707 mt7996_mac_update_stats(struct mt7996_phy * phy) mt7996_mac_update_stats() argument
2893 struct mt7996_phy *phy; mt7996_mac_work() local
2923 mt7996_dfs_stop_radar_detector(struct mt7996_phy * phy) mt7996_dfs_stop_radar_detector() argument
2958 mt7996_dfs_start_radar_detector(struct mt7996_phy * phy) mt7996_dfs_start_radar_detector() argument
2978 mt7996_dfs_init_radar_specs(struct mt7996_phy * phy) mt7996_dfs_init_radar_specs() argument
3011 mt7996_dfs_init_radar_detector(struct mt7996_phy * phy) mt7996_dfs_init_radar_detector() argument
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