Lines Matching +full:t +full:- +full:phy
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
14 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2)
17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
65 if (!wcid || !wcid->sta)
71 if (wcid->phy_idx == band_idx)
75 msta = msta_link->sta;
76 if (!msta || !msta->vif)
79 mvif = msta->vif;
80 for (i = 0; i < ARRAY_SIZE(mvif->mt76.link); i++) {
83 mlink = rcu_dereference(mvif->mt76.link[i]);
87 if (mlink->band_idx != band_idx)
90 msta_link = rcu_dereference(msta->link[i]);
94 return &msta_link->wcid;
131 spin_lock_bh(&dev->mt76.sta_poll_lock);
132 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list);
133 spin_unlock_bh(&dev->mt76.sta_poll_lock);
143 spin_lock_bh(&dev->mt76.sta_poll_lock);
145 spin_unlock_bh(&dev->mt76.sta_poll_lock);
151 msta = msta_link->sta;
152 wcid = &msta_link->wcid;
153 list_del_init(&wcid->poll_list);
154 spin_unlock_bh(&dev->mt76.sta_poll_lock);
156 idx = wcid->idx;
162 u32 tx_last = msta_link->airtime_ac[i];
163 u32 rx_last = msta_link->airtime_ac[i + 4];
165 msta_link->airtime_ac[i] = mt76_rr(dev, addr);
166 msta_link->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
168 tx_time[i] = msta_link->airtime_ac[i] - tx_last;
169 rx_time[i] = msta_link->airtime_ac[i + 4] - rx_last;
180 memset(msta_link->airtime_ac, 0,
181 sizeof(msta_link->airtime_ac));
184 if (!wcid->sta)
210 mlink = rcu_dereference(msta->vif->mt76.link[wcid->link_id]);
215 msta_link->ack_signal =
216 mt76_rx_signal(mphy->antenna_mask,
220 ewma_avg_signal_add(&msta_link->avg_ack_signal,
221 -msta_link->ack_signal);
230 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
231 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap);
232 struct mt7996_sta_link *msta_link = (void *)status->wcid;
233 struct mt7996_sta *msta = msta_link->sta;
235 __le32 *rxd = (__le32 *)skb->data;
243 return -EINVAL;
246 return -EINVAL;
248 if (!msta || !msta->vif)
249 return -EINVAL;
251 sta = wcid_to_sta(status->wcid);
252 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
253 link_conf = rcu_dereference(vif->link_conf[msta_link->wcid.link_id]);
255 return -EINVAL;
263 ether_addr_copy(hdr.addr1, vif->addr);
264 ether_addr_copy(hdr.addr2, sta->addr);
268 ether_addr_copy(hdr.addr3, link_conf->bssid);
271 ether_addr_copy(hdr.addr3, eth_hdr->h_source);
274 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
277 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
278 ether_addr_copy(hdr.addr4, eth_hdr->h_source);
281 return -EINVAL;
284 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2);
285 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) ||
286 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX))
288 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN)
307 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6);
341 i = mt76_get_rate(&dev->mt76, sband, i, cck);
345 status->encoding = RX_ENC_HT;
347 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
349 return -EINVAL;
352 status->nss = nss;
353 status->encoding = RX_ENC_VHT;
355 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
357 return -EINVAL;
363 status->nss = nss;
364 status->encoding = RX_ENC_HE;
368 status->he_gi = gi;
370 status->he_dcm = dcm;
375 status->nss = nss;
376 status->encoding = RX_ENC_EHT;
380 status->eht.gi = gi;
383 return -EINVAL;
385 status->rate_idx = i;
393 status->bw = RATE_INFO_BW_HE_RU;
394 status->he_ru =
397 status->bw = RATE_INFO_BW_40;
401 status->bw = RATE_INFO_BW_80;
404 status->bw = RATE_INFO_BW_160;
406 /* rxv reports bw 320-1 and 320-2 separately */
409 status->bw = RATE_INFO_BW_320;
412 return -EINVAL;
415 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
417 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
430 if (!msta || !msta->vif)
439 vif = container_of((void *)msta->vif, struct ieee80211_vif,
442 skb->dev = wdev->netdev;
444 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb,
453 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
454 struct mt76_phy *mphy = &dev->mt76.phy;
455 struct mt7996_phy *phy = &dev->phy;
457 __le32 *rxd = (__le32 *)skb->data;
465 u32 csum_status = *(u32 *)skb->cb;
479 hw_aggr = status->aggr;
483 mphy = dev->mt76.phys[band_idx];
484 phy = mphy->priv;
485 status->phy_idx = mphy->band_idx;
487 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
488 return -EINVAL;
491 return -EINVAL;
495 return -EINVAL;
499 status->flag |= RX_FLAG_ONLY_MONITOR;
503 status->wcid = mt7996_rx_get_wcid(dev, idx, band_idx);
505 if (status->wcid) {
508 msta_link = container_of(status->wcid, struct mt7996_sta_link,
510 msta = msta_link->sta;
511 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid);
514 status->freq = mphy->chandef.chan->center_freq;
515 status->band = mphy->chandef.chan->band;
516 if (status->band == NL80211_BAND_5GHZ)
517 sband = &mphy->sband_5g.sband;
518 else if (status->band == NL80211_BAND_6GHZ)
519 sband = &mphy->sband_6g.sband;
521 sband = &mphy->sband_2g.sband;
523 if (!sband->channels)
524 return -EINVAL;
528 skb->ip_summed = CHECKSUM_UNNECESSARY;
531 status->flag |= RX_FLAG_FAILED_FCS_CRC;
534 status->flag |= RX_FLAG_MMIC_ERROR;
538 status->flag |= RX_FLAG_DECRYPTED;
539 status->flag |= RX_FLAG_IV_STRIPPED;
540 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
546 return -EINVAL;
558 if ((u8 *)rxd - skb->data >= skb->len)
559 return -EINVAL;
565 if (status->flag & RX_FLAG_DECRYPTED) {
577 status->iv[0] = data[5];
578 status->iv[1] = data[4];
579 status->iv[2] = data[3];
580 status->iv[3] = data[2];
581 status->iv[4] = data[1];
582 status->iv[5] = data[0];
589 if ((u8 *)rxd - skb->data >= skb->len)
590 return -EINVAL;
594 status->timestamp = le32_to_cpu(rxd[0]);
595 status->flag |= RX_FLAG_MACTIME_START;
598 status->flag |= RX_FLAG_AMPDU_DETAILS;
600 /* all subframes of an A-MPDU have the same timestamp */
601 if (phy->rx_ampdu_ts != status->timestamp) {
602 if (!++phy->ampdu_ref)
603 phy->ampdu_ref++;
605 phy->rx_ampdu_ts = status->timestamp;
607 status->ampdu_ref = phy->ampdu_ref;
611 if ((u8 *)rxd - skb->data >= skb->len)
612 return -EINVAL;
615 /* RXD Group 3 - P-RXV */
622 if ((u8 *)rxd - skb->data >= skb->len)
623 return -EINVAL;
627 status->chains = mphy->antenna_mask;
628 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3);
629 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3);
630 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3);
631 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3);
633 /* RXD Group 5 - C-RXV */
636 if ((u8 *)rxd - skb->data >= skb->len)
637 return -EINVAL;
646 status->amsdu = !!amsdu_info;
647 if (status->amsdu) {
648 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME;
649 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
654 * This check fixes vulnerabilities, like CVE-2020-26145.
658 return -EINVAL;
660 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
663 return -EINVAL;
669 if (!hdr_trans && status->amsdu && !(ieee80211_has_a4(fc) && is_mesh)) {
673 * the hardware will insert an extra 2-byte field
675 * type field. This happens either when the LLC-SNAP
680 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q)
687 memmove(skb->data + 2, skb->data, pad_start);
702 fc = hdr->frame_control;
706 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
710 * de-amsdu, so here needs to clear amsdu present bit
713 if (ieee80211_has_a4(fc) && is_mesh && status->amsdu)
716 skb_set_mac_header(skb, (unsigned char *)hdr - skb->data);
718 status->flag |= RX_FLAG_8023;
719 mt7996_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb,
721 mt76_npu_check_ppe(&dev->mt76, skb, *info);
724 if (rxv && !(status->flag & RX_FLAG_8023)) {
725 switch (status->encoding) {
737 if (!status->wcid || !ieee80211_is_data_qos(fc) || hw_aggr)
740 status->aggr = unicast &&
742 status->qos_ctl = qos_ctl;
743 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
752 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
758 if (wcid->sta) {
761 wmm = sta->wme;
767 ethertype = get_unaligned_be16(&skb->data[12]);
781 if (wcid->amsdu)
791 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
792 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
794 bool multicast = is_multicast_ether_addr(hdr->addr1);
795 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
796 __le16 fc = hdr->frame_control, sc = hdr->seq_ctrl;
803 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
804 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) {
805 if (is_mt7990(&dev->mt76))
811 } else if (ieee80211_is_mgmt(hdr->frame_control)) {
821 info->flags & IEEE80211_TX_CTL_USE_MINRATE)
824 if (is_mt7990(&dev->mt76) && ieee80211_is_beacon(fc) &&
825 (wcid->hw_key_idx2 == 6 || wcid->hw_key_idx2 == 7))
858 if (multicast && ieee80211_vif_is_mld(info->control.vif)) {
864 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
865 if (ieee80211_is_back_req(hdr->frame_control)) {
868 bar = (struct ieee80211_bar *)skb->data;
869 seqno = le16_to_cpu(bar->start_seq_num);
878 if (ieee80211_vif_is_mld(info->control.vif) &&
879 (multicast || unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))))
883 ieee80211_vif_is_mld(info->control.vif)) {
888 if (!wcid->sta && ieee80211_is_mgmt(fc))
897 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
899 struct ieee80211_vif *vif = info->control.vif;
900 u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
902 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
913 if (wcid != &dev->mt76.global_wcid)
914 link_id = wcid->link_id;
916 link_id = u32_get_bits(info->control.flags,
919 mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL;
921 if (wcid->offchannel)
922 mlink = rcu_dereference(mvif->mt76.offchannel_link);
924 mlink = rcu_dereference(mvif->mt76.link[link_id]);
928 omac_idx = mlink->omac_idx;
929 wmm_idx = mlink->wmm_idx;
930 band_idx = mlink->band_idx;
948 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
953 val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
966 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
979 skb->protocol == cpu_to_be16(ETH_P_PAE))
982 if (is_mt7996(&dev->mt76))
984 else if (is_8023 || !ieee80211_is_mgmt(hdr->frame_control))
996 bool mcast = ieee80211_is_data(hdr->frame_control) &&
997 is_multicast_ether_addr(hdr->addr1);
1001 if (mcast && mlink->mcast_rates_idx)
1002 idx = mlink->mcast_rates_idx;
1003 else if (beacon && mlink->beacon_rates_idx)
1004 idx = mlink->beacon_rates_idx;
1006 idx = mlink->basic_rates_idx;
1020 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1022 if (ieee80211_is_mgmt(hdr->frame_control))
1027 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))
1030 if (ieee80211_has_a4(hdr->frame_control) &&
1031 !ieee80211_is_data_present(hdr->frame_control))
1043 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1045 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1046 struct ieee80211_key_conf *key = info->control.hw_key;
1047 struct ieee80211_vif *vif = info->control.vif;
1048 struct mt7996_vif *mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL;
1049 struct mt7996_sta *msta = sta ? (struct mt7996_sta *)sta->drv_priv : NULL;
1051 struct mt76_txwi_cache *t;
1052 int id, i, pid, nbuf = tx_info->nbuf - 1;
1053 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
1058 if (unlikely(tx_info->skb->len <= ETH_HLEN))
1059 return -EINVAL;
1062 wcid = &dev->mt76.global_wcid;
1064 if ((is_8023 || ieee80211_is_data_qos(hdr->frame_control)) && sta->mlo &&
1065 likely(tx_info->skb->protocol != cpu_to_be16(ETH_P_PAE))) {
1066 u8 tid = tx_info->skb->priority & IEEE80211_QOS_CTL_TID_MASK;
1068 link_id = (tid % 2) ? msta->seclink_id : msta->deflink_id;
1070 link_id = u32_get_bits(info->control.flags,
1074 if (link_id != wcid->link_id && link_id != IEEE80211_LINK_UNSPECIFIED) {
1077 rcu_dereference(msta->link[link_id]);
1080 wcid = &msta_link->wcid;
1082 mlink = rcu_dereference(mvif->mt76.link[link_id]);
1083 if (mlink && mlink->wcid)
1084 wcid = mlink->wcid;
1088 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
1089 t->skb = tx_info->skb;
1091 id = mt76_token_consume(mdev, &t);
1099 if (tx_info->skb->protocol == cpu_to_be16(ETH_P_PAE) && sta->mlo) {
1100 struct ieee80211_hdr *hdr = (void *)tx_info->skb->data;
1104 link_conf = rcu_dereference(vif->link_conf[wcid->link_id]);
1106 return -EINVAL;
1108 link_sta = rcu_dereference(sta->link[wcid->link_id]);
1110 return -EINVAL;
1112 dma_sync_single_for_cpu(mdev->dma_dev, tx_info->buf[1].addr,
1113 tx_info->buf[1].len, DMA_TO_DEVICE);
1115 memcpy(hdr->addr1, link_sta->addr, ETH_ALEN);
1116 memcpy(hdr->addr2, link_conf->addr, ETH_ALEN);
1117 if (ieee80211_has_a4(hdr->frame_control)) {
1118 memcpy(hdr->addr3, sta->addr, ETH_ALEN);
1119 memcpy(hdr->addr4, vif->addr, ETH_ALEN);
1120 } else if (ieee80211_has_tods(hdr->frame_control)) {
1121 memcpy(hdr->addr3, sta->addr, ETH_ALEN);
1122 } else if (ieee80211_has_fromds(hdr->frame_control)) {
1123 memcpy(hdr->addr3, vif->addr, ETH_ALEN);
1126 dma_sync_single_for_device(mdev->dma_dev, tx_info->buf[1].addr,
1127 tx_info->buf[1].len, DMA_TO_DEVICE);
1130 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1134 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key,
1151 tx_info->skb->priority &
1154 ptr[2] = cpu_to_le32(tx_info->buf[1].addr & 0xFFFFFFFF);
1156 val = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[1].len) |
1160 tx_info->buf[1].addr >> 32);
1170 len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len);
1173 tx_info->buf[i + 1].addr >> 32);
1176 txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
1177 txp->fw.len[i] = cpu_to_le16(len);
1179 txp->fw.nbuf = nbuf;
1181 txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST);
1184 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD);
1187 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
1189 if (!is_8023 && mt7996_tx_use_mgmt(dev, tx_info->skb))
1190 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
1193 if (wcid->offchannel)
1194 mlink = rcu_dereference(mvif->mt76.offchannel_link);
1196 mlink = rcu_dereference(mvif->mt76.link[wcid->link_id]);
1198 txp->fw.bss_idx = mlink ? mlink->idx : mvif->deflink.mt76.idx;
1201 txp->fw.token = cpu_to_le16(id);
1202 txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff);
1205 tx_info->skb = NULL;
1208 tx_info->buf[1].len = MT_CT_PARSE_LEN;
1209 tx_info->buf[1].skip_unmap = true;
1210 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
1231 txp->token = cpu_to_le16(token_id);
1232 txp->nbuf = 1;
1233 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp));
1243 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
1246 if (!(link_sta->ht_cap.ht_supported || link_sta->he_cap.has_he))
1249 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
1255 (link_sta->sta->wme ? IEEE80211_STYPE_QOS_DATA
1263 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1265 fc = le16_to_cpu(hdr->frame_control) &
1272 if (!test_and_set_bit(tid, &wcid->ampdu_state))
1273 ieee80211_start_tx_ba_session(link_sta->sta, tid, 0);
1277 mt7996_txwi_free(struct mt7996_dev *dev, struct mt76_txwi_cache *t,
1281 struct mt76_dev *mdev = &dev->mt76;
1285 mt76_connac_txp_skb_unmap(mdev, t);
1286 if (!t->skb)
1289 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t);
1291 wcid_idx = wcid->idx;
1292 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) {
1296 msta = (void *)link_sta->sta->drv_priv;
1297 mt7996_tx_check_aggr(link_sta, &msta->deflink.wcid,
1298 t->skb);
1304 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list);
1307 t->skb = NULL;
1308 mt76_put_txwi(mdev, t);
1315 struct mt76_dev *mdev = &dev->mt76;
1316 struct mt76_phy *phy2 = mdev->phys[MT_BAND1];
1317 struct mt76_phy *phy3 = mdev->phys[MT_BAND2];
1329 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1330 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1332 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_PSD], false);
1333 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_BE], false);
1336 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_PSD], false);
1337 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_BE], false);
1370 link_sta = rcu_dereference(sta->link[wcid->link_id]);
1374 msta = (struct mt7996_sta *)sta->drv_priv;
1375 valid_links = sta->valid_links ?: BIT(0);
1382 msta_link = rcu_dereference(msta->link[id]);
1386 mt76_wcid_add_poll(&dev->mt76,
1387 &msta_link->wcid);
1402 FIELD_GET(MT_TXFREE_INFO_COUNT, info) - 1;
1406 wcid->stats.tx_retries += tx_retries;
1407 wcid->stats.tx_failed += tx_failed;
1429 mt76_set_tx_blocked(&dev->mt76, false);
1431 mt76_worker_schedule(&dev->mt76.tx_worker);
1443 struct mt76_sta_stats *stats = &wcid->stats;
1445 struct mt76_dev *mdev = &dev->mt76;
1464 info->flags |= IEEE80211_TX_STAT_ACK;
1466 info->status.ampdu_len = 1;
1467 info->status.ampdu_ack_len =
1468 !!(info->flags & IEEE80211_TX_STAT_ACK);
1470 info->status.rates[0].idx = -1;
1474 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && wcid->sta) {
1492 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss))
1493 stats->tx_nss[rate.nss - 1]++;
1494 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs))
1495 stats->tx_mcs[rate.mcs]++;
1503 mphy = mt76_dev_phy(mdev, wcid->phy_idx);
1505 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1506 sband = &mphy->sband_5g.sband;
1507 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ)
1508 sband = &mphy->sband_6g.sband;
1510 sband = &mphy->sband_2g.sband;
1512 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck);
1513 rate.legacy = sband->bitrates[rate.mcs].bitrate;
1521 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI)
1529 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI)
1539 rate.he_gi = wcid->rate.he_gi;
1549 rate.eht_gi = wcid->rate.eht_gi;
1556 stats->tx_mode[mode]++;
1561 stats->tx_bw[4]++;
1565 stats->tx_bw[3]++;
1569 stats->tx_bw[2]++;
1573 stats->tx_bw[1]++;
1577 stats->tx_bw[0]++;
1580 wcid->rate = rate;
1612 if (!wcid->sta)
1616 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid);
1658 __le32 *rxd = (__le32 *)skb->data;
1659 __le32 *end = (__le32 *)&skb->data[skb->len];
1673 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2) &&
1679 mt7996_mac_tx_free(dev, skb->data, skb->len);
1691 mt7996_debugfs_rx_fw_monitor(dev, skb->data, skb->len);
1696 mt76_rx(&dev->mt76, q, skb);
1711 spin_lock(&dev->wed_rro.lock);
1713 if (!list_empty(&dev->wed_rro.page_cache)) {
1714 p = list_first_entry(&dev->wed_rro.page_cache,
1716 list_del(&p->list);
1719 spin_unlock(&dev->wed_rro.lock);
1732 INIT_LIST_HEAD(&p->list);
1741 if (p->buf) {
1742 mt76_put_page_pool_buf(p->buf, false);
1743 p->buf = NULL;
1746 spin_lock(&dev->wed_rro.lock);
1747 list_add(&p->list, &dev->wed_rro.page_cache);
1748 spin_unlock(&dev->wed_rro.lock);
1760 if (p->buf)
1761 mt76_put_page_pool_buf(p->buf, false);
1787 spin_lock(&dev->wed_rro.lock);
1789 list_for_each_entry_safe(p, tmp, &dev->wed_rro.page_map[hash],
1791 if (p->dma_addr == dma_addr) {
1792 list_del(&p->list);
1798 spin_unlock(&dev->wed_rro.lock);
1807 for (i = 0; i < dev->mt76.rx_token_size; i++) {
1808 struct mt76_txwi_cache *t;
1810 t = mt76_rx_token_release(&dev->mt76, i);
1811 if (!t || !t->ptr)
1814 mt76_put_page_pool_buf(t->ptr, false);
1815 t->dma_addr = 0;
1816 t->ptr = NULL;
1818 mt76_put_rxwi(&dev->mt76, t);
1829 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) {
1830 list_for_each_entry_safe(p, tmp, &dev->wed_rro.page_map[i],
1832 list_del_init(&p->list);
1833 if (p->buf)
1834 mt76_put_page_pool_buf(p->buf, false);
1853 pinfo->data |= cpu_to_le32(FIELD_PREP(MSDU_PAGE_INFO_OWNER_MASK, 1));
1856 return -ENOMEM;
1858 p->buf = data;
1859 p->dma_addr = dma_addr;
1860 p->q = q;
1864 spin_lock(&dev->wed_rro.lock);
1865 list_add_tail(&p->list, &dev->wed_rro.page_map[hash]);
1866 spin_unlock(&dev->wed_rro.lock);
1878 addr = dev->wed_rro.session.ptr;
1881 addr = dev->wed_rro.addr_elem[idx].ptr;
1897 u32 cmd_data0 = le32_to_cpu(cmd->data0);
1898 u32 cmd_data1 = le32_to_cpu(cmd->data1);
1912 struct mt76_txwi_cache *t;
1924 data = le32_to_cpu(e->data);
1930 e->data |= cpu_to_le32(val);
1938 dma_addr |= le32_to_cpu(e->head_low);
1947 dma_sync_single_for_cpu(mdev->dma_dev, p->dma_addr,
1948 SKB_WITH_OVERHEAD(p->q->buf_size),
1949 page_pool_get_dma_dir(p->q->page_pool));
1950 pinfo = (struct mt7996_msdu_page_info *)p->buf;
1953 rxd = &pinfo->rxd[j % MT7996_MAX_HIF_RXD_IN_PG];
1955 le32_to_cpu(rxd->data1));
1958 le32_to_cpu(rxd->data4));
1959 t = mt76_rx_token_release(mdev, rx_token_id);
1960 if (!t)
1963 qid = t->qid;
1964 buf = t->ptr;
1965 q = &mdev->q_rx[qid];
1966 dma_sync_single_for_cpu(mdev->dma_dev, t->dma_addr,
1967 SKB_WITH_OVERHEAD(q->buf_size),
1968 page_pool_get_dma_dir(q->page_pool));
1970 t->dma_addr = 0;
1971 t->ptr = NULL;
1972 mt76_put_rxwi(mdev, t);
1976 if (q->rx_head)
1977 data_len = q->buf_size;
1979 data_len = SKB_WITH_OVERHEAD(q->buf_size);
1981 if (data_len < len + q->buf_offset) {
1982 dev_kfree_skb(q->rx_head);
1984 q->rx_head = NULL;
1989 le32_to_cpu(rxd->data1));
1990 if (q->rx_head) {
1991 /* TODO: Take into account non-linear skb. */
1994 dev_kfree_skb(q->rx_head);
1995 q->rx_head = NULL;
2003 skb = build_skb(buf, q->buf_size);
2007 skb_reserve(skb, q->buf_offset);
2017 q->rx_head = skb;
2021 status = (struct mt76_rx_status *)skb->cb;
2023 status->aggr = true;
2031 le32_to_cpu(pinfo->data));
2033 dma_addr |= le32_to_cpu(pinfo->pg_low);
2035 dma_addr = le32_to_cpu(pinfo->pg_low);
2062 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy)
2064 struct mt7996_dev *dev = phy->dev;
2065 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx);
2071 void mt7996_mac_reset_counters(struct mt7996_phy *phy)
2073 struct mt7996_dev *dev = phy->dev;
2074 u8 band_idx = phy->mt76->band_idx;
2080 phy->mt76->survey_time = ktime_get_boottime();
2082 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats));
2088 mt7996_mcu_get_chan_mib_info(phy, true);
2091 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy)
2093 s16 coverage_class = phy->coverage_class;
2094 struct mt7996_dev *dev = phy->dev;
2102 u8 band_idx = phy->mt76->band_idx;
2105 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
2109 coverage_class = max_t(s16, dev->phy.coverage_class,
2110 phy2->coverage_class);
2114 phy3->coverage_class);
2135 mt7996_phy_get_nf(struct mt7996_phy *phy, u8 band_idx)
2138 struct mt7996_dev *dev = phy->dev;
2142 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) {
2157 struct mt7996_phy *phy = mphy->priv;
2158 struct mt76_channel_state *state = mphy->chan_state;
2161 mt7996_mcu_get_chan_mib_info(phy, false);
2163 nf = mt7996_phy_get_nf(phy, mphy->band_idx);
2164 if (!phy->noise)
2165 phy->noise = nf << 4;
2167 phy->noise += nf - (phy->noise >> 4);
2169 state->noise = -(phy->noise >> 4);
2177 ret = wait_event_timeout(dev->reset_wait,
2178 (READ_ONCE(dev->recovery.state) & state),
2189 struct mt7996_phy *phy = priv;
2190 struct mt7996_dev *dev = phy->dev;
2194 switch (vif->type) {
2207 if (!link || link->phy != phy)
2210 mt7996_mcu_add_beacon(dev->mt76.hw, vif, link_conf,
2211 link_conf->enable_beacon);
2215 void mt7996_mac_update_beacons(struct mt7996_phy *phy)
2217 ieee80211_iterate_active_interfaces(phy->mt76->hw,
2219 mt7996_update_vif_beacon, phy);
2227 mt7996_mac_update_beacons(&dev->phy);
2229 phy2 = dev->mt76.phys[MT_BAND1];
2231 mt7996_mac_update_beacons(phy2->priv);
2233 phy3 = dev->mt76.phys[MT_BAND2];
2235 mt7996_mac_update_beacons(phy3->priv);
2243 spin_lock_bh(&dev->mt76.token_lock);
2244 idr_for_each_entry(&dev->mt76.token, txwi, id) {
2246 dev->mt76.token_count--;
2248 spin_unlock_bh(&dev->mt76.token_lock);
2249 idr_destroy(&dev->mt76.token);
2255 struct mt76_dev *mdev = &dev->mt76;
2256 struct mt7996_phy *phy;
2259 if (dev->hif2) {
2264 if (dev_is_pci(mdev->dev)) {
2266 if (dev->hif2)
2270 set_bit(MT76_MCU_RESET, &dev->mphy.state);
2271 mt7996_for_each_phy(dev, phy)
2272 set_bit(MT76_RESET, &phy->mt76->state);
2273 wake_up(&dev->mt76.mcu.wait);
2276 mt7996_for_each_phy(dev, phy)
2277 mt76_txq_schedule_all(phy->mt76);
2280 mt76_worker_disable(&dev->mt76.tx_worker);
2282 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
2283 mt76_queue_is_wed_rro(&mdev->q_rx[i]))
2286 if (mdev->q_rx[i].ndesc)
2287 napi_disable(&dev->mt76.napi[i]);
2289 napi_disable(&dev->mt76.tx_napi);
2293 idr_init(&dev->mt76.token);
2298 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
2299 mt76_queue_is_wed_rro(&mdev->q_rx[i]))
2302 if (mdev->q_rx[i].ndesc) {
2303 napi_enable(&dev->mt76.napi[i]);
2305 napi_schedule(&dev->mt76.napi[i]);
2309 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
2310 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
2312 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask);
2314 if (dev->hif2) {
2315 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask);
2318 if (dev_is_pci(mdev->dev)) {
2320 if (dev->hif2)
2329 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
2331 u32 wed_irq_mask = dev->mt76.mmio.irqmask |
2335 mt76_for_each_q_rx(&dev->mt76, i) {
2336 if (mt76_queue_is_wed_rro_ind(&dev->mt76.q_rx[i]) ||
2337 mt76_queue_is_wed_rro_msdu_pg(&dev->mt76.q_rx[i]))
2342 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask,
2348 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) {
2351 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2,
2361 mt7996_for_each_phy(dev, phy)
2362 mt7996_init_txpower(phy);
2367 mt7996_for_each_phy(dev, phy) {
2368 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
2371 ret = mt7996_run(phy);
2378 mt7996_for_each_phy(dev, phy)
2379 clear_bit(MT76_RESET, &phy->mt76->state);
2381 napi_enable(&dev->mt76.tx_napi);
2383 napi_schedule(&dev->mt76.tx_napi);
2386 mt76_worker_enable(&dev->mt76.tx_worker);
2393 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv;
2397 for (i = 0; i < ARRAY_SIZE(msta->link); i++) {
2400 msta_link = rcu_replace_pointer(msta->link[i], msta_link,
2401 lockdep_is_held(&dev->mt76.mutex));
2407 if (msta->deflink_id == i) {
2408 msta->deflink_id = IEEE80211_LINK_UNSPECIFIED;
2419 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2420 struct mt76_vif_data *mvif = mlink->mvif;
2425 for (i = 0; i < ARRAY_SIZE(mvif->link); i++) {
2427 mlink = mt76_dereference(mvif->link[i], &dev->mt76);
2428 if (!mlink || mlink == (struct mt76_vif_link *)vif->drv_priv)
2431 rcu_assign_pointer(mvif->link[i], NULL);
2441 struct mt7996_phy *phy;
2445 dev->recovery.hw_full_reset = true;
2447 wake_up(&dev->mt76.mcu.wait);
2450 cancel_work_sync(&dev->wed_rro.work);
2451 mt7996_for_each_phy(dev, phy)
2452 cancel_delayed_work_sync(&phy->mt76->mac_work);
2454 mt76_abort_scan(&dev->mt76);
2456 mutex_lock(&dev->mt76.mutex);
2463 dev_err(dev->mt76.dev, "chip full reset failed\n");
2465 mt7996_for_each_phy(dev, phy)
2466 phy->omac_mask = 0;
2472 mt76_reset_device(&dev->mt76);
2474 INIT_LIST_HEAD(&dev->sta_rc_list);
2475 INIT_LIST_HEAD(&dev->twt_list);
2477 spin_lock_bh(&dev->wed_rro.lock);
2478 list_splice_init(&dev->wed_rro.poll_list, &list);
2479 spin_unlock_bh(&dev->wed_rro.lock);
2486 list_del_init(&e->list);
2490 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA);
2491 dev->mt76.global_wcid.idx = i;
2492 dev->recovery.hw_full_reset = false;
2494 mutex_unlock(&dev->mt76.mutex);
2503 struct mt7996_phy *phy;
2510 if (dev->recovery.restart) {
2515 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT)
2516 dev->recovery.wa_reset_count++;
2518 dev->recovery.wm_reset_count++;
2529 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE;
2530 dev->recovery.restart = false;
2534 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA))
2537 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.",
2538 wiphy_name(hw->wiphy));
2540 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2))
2541 mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2);
2543 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
2544 mtk_wed_device_stop(&dev->mt76.mmio.wed);
2548 set_bit(MT76_RESET, &dev->mphy.state);
2549 set_bit(MT76_MCU_RESET, &dev->mphy.state);
2550 mt76_abort_scan(&dev->mt76);
2551 wake_up(&dev->mt76.mcu.wait);
2553 cancel_work_sync(&dev->wed_rro.work);
2554 mt7996_for_each_phy(dev, phy) {
2555 mt76_abort_roc(phy->mt76);
2556 set_bit(MT76_RESET, &phy->mt76->state);
2557 cancel_delayed_work_sync(&phy->mt76->mac_work);
2560 mt76_worker_disable(&dev->mt76.tx_worker);
2561 mt76_for_each_q_rx(&dev->mt76, i) {
2562 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
2563 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]))
2566 napi_disable(&dev->mt76.napi[i]);
2568 napi_disable(&dev->mt76.tx_napi);
2570 mutex_lock(&dev->mt76.mutex);
2580 idr_init(&dev->mt76.token);
2592 if (!is_mt7996(&dev->mt76) && dev->mt76.hwrro_mode == MT76_HWRRO_V3)
2595 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2597 dev->mt76.mmio.irqmask;
2600 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask,
2606 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) {
2608 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2,
2612 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
2613 mt7996_for_each_phy(dev, phy)
2614 clear_bit(MT76_RESET, &phy->mt76->state);
2616 mt76_for_each_q_rx(&dev->mt76, i) {
2617 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
2618 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]))
2621 napi_enable(&dev->mt76.napi[i]);
2623 napi_schedule(&dev->mt76.napi[i]);
2627 tasklet_schedule(&dev->mt76.irq_tasklet);
2629 mt76_worker_enable(&dev->mt76.tx_worker);
2631 napi_enable(&dev->mt76.tx_napi);
2633 napi_schedule(&dev->mt76.tx_napi);
2639 mutex_unlock(&dev->mt76.mutex);
2643 mt7996_for_each_phy(dev, phy)
2644 ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work,
2646 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.",
2647 wiphy_name(dev->mt76.hw->wiphy));
2664 mutex_lock(&dev->dump_mutex);
2668 mutex_unlock(&dev->dump_mutex);
2673 if (!mem_region || !crash_data->memdump_buf_len) {
2674 mutex_unlock(&dev->dump_mutex);
2678 buf = crash_data->memdump_buf;
2679 buf_len = crash_data->memdump_buf_len;
2684 if (mem_region->len > buf_len) {
2685 dev_warn(dev->mt76.dev, "%s len %zu is too large\n",
2686 mem_region->name, mem_region->len);
2693 buf_len -= sizeof(*hdr);
2695 mt7996_memcpy_fromio(dev, buf, mem_region->start,
2696 mem_region->len);
2698 hdr->start = mem_region->start;
2699 hdr->len = mem_region->len;
2701 if (!mem_region->len)
2705 buf += mem_region->len;
2706 buf_len -= mem_region->len;
2711 mutex_unlock(&dev->dump_mutex);
2716 queue_work(dev->mt76.wq, &dev->reset_work);
2721 if (!dev->recovery.hw_init_done)
2724 if (dev->recovery.hw_full_reset)
2728 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) {
2729 dev->recovery.restart = true;
2730 dev_info(dev->mt76.dev,
2732 wiphy_name(dev->mt76.hw->wiphy));
2735 queue_work(dev->mt76.wq, &dev->dump_work);
2739 queue_work(dev->mt76.wq, &dev->reset_work);
2740 wake_up(&dev->reset_wait);
2743 void mt7996_mac_update_stats(struct mt7996_phy *phy)
2745 struct mt76_mib_stats *mib = &phy->mib;
2746 struct mt7996_dev *dev = phy->dev;
2747 u8 band_idx = phy->mt76->band_idx;
2752 mib->fcs_err_cnt += cnt;
2755 mib->rx_fifo_full_cnt += cnt;
2758 mib->rx_mpdu_cnt += cnt;
2761 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt);
2764 mib->rx_vector_mismatch_cnt += cnt;
2767 mib->rx_delimiter_fail_cnt += cnt;
2770 mib->rx_len_mismatch_cnt += cnt;
2773 mib->tx_ampdu_cnt += cnt;
2776 mib->tx_stop_q_empty_cnt += cnt;
2779 mib->tx_mpdu_attempts_cnt += cnt;
2782 mib->tx_mpdu_success_cnt += cnt;
2785 mib->rx_ampdu_cnt += cnt;
2788 mib->rx_ampdu_bytes_cnt += cnt;
2791 mib->rx_ampdu_valid_subframe_cnt += cnt;
2794 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt;
2797 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT, cnt);
2800 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT, cnt);
2803 mib->rx_pfdrop_cnt += cnt;
2806 mib->rx_vec_queue_overflow_drop_cnt += cnt;
2809 mib->rx_ba_cnt += cnt;
2812 mib->tx_bf_ebf_ppdu_cnt += cnt;
2815 mib->tx_bf_ibf_ppdu_cnt += cnt;
2818 mib->tx_mu_bf_cnt += cnt;
2821 mib->tx_mu_mpdu_cnt += cnt;
2824 mib->tx_mu_acked_mpdu_cnt += cnt;
2827 mib->tx_su_acked_mpdu_cnt += cnt;
2830 mib->tx_bf_rx_fb_ht_cnt += cnt;
2831 mib->tx_bf_rx_fb_all_cnt += cnt;
2834 mib->tx_bf_rx_fb_vht_cnt += cnt;
2835 mib->tx_bf_rx_fb_all_cnt += cnt;
2838 mib->tx_bf_rx_fb_he_cnt += cnt;
2839 mib->tx_bf_rx_fb_all_cnt += cnt;
2842 mib->tx_bf_rx_fb_eht_cnt += cnt;
2843 mib->tx_bf_rx_fb_all_cnt += cnt;
2846 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt);
2847 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt);
2848 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt);
2851 mib->tx_bf_fb_trig_cnt += cnt;
2854 mib->tx_bf_fb_cpl_cnt += cnt;
2856 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
2858 mib->tx_amsdu[i] += cnt;
2859 mib->tx_amsdu_cnt += cnt;
2864 mib->rts_cnt += cnt;
2868 mib->rts_retries_cnt += cnt;
2872 mib->ba_miss_cnt += cnt;
2876 mib->ack_fail_cnt += cnt;
2880 phy->mt76->aggr_stats[i] += cnt;
2893 mutex_lock(&dev->mt76.mutex);
2895 spin_lock_bh(&dev->mt76.sta_poll_lock);
2896 list_splice_init(&dev->sta_rc_list, &list);
2901 list_del_init(&msta_link->rc_list);
2903 changed = msta_link->changed;
2904 msta_link->changed = 0;
2905 mvif = msta_link->sta->vif;
2909 spin_unlock_bh(&dev->mt76.sta_poll_lock);
2914 mt7996_mcu_add_rate_ctrl(dev, msta_link->sta, vif,
2915 msta_link->wcid.link_id,
2919 mt7996_mcu_set_fixed_field(dev, msta_link->sta, NULL,
2920 msta_link->wcid.link_id,
2923 spin_lock_bh(&dev->mt76.sta_poll_lock);
2926 spin_unlock_bh(&dev->mt76.sta_poll_lock);
2928 mutex_unlock(&dev->mt76.mutex);
2933 struct mt7996_phy *phy;
2938 phy = mphy->priv;
2940 mutex_lock(&mphy->dev->mutex);
2943 if (++mphy->mac_work_count == 5) {
2944 mphy->mac_work_count = 0;
2946 mt7996_mac_update_stats(phy);
2948 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_RATE);
2949 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) {
2950 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_ADM_STAT);
2951 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_MSDU_COUNT);
2955 mutex_unlock(&mphy->dev->mutex);
2957 mt76_tx_status_check(mphy->dev, false);
2959 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
2963 static void mt7996_dfs_stop_radar_detector(struct mt7996_phy *phy)
2965 struct mt7996_dev *dev = phy->dev;
2966 int rdd_idx = mt7996_get_rdd_idx(phy, false);
2978 switch (dev->mt76.region) {
2998 static int mt7996_dfs_start_radar_detector(struct mt7996_phy *phy)
3000 struct mt7996_dev *dev = phy->dev;
3003 rdd_idx = mt7996_get_rdd_idx(phy, false);
3005 return -EINVAL;
3018 mt7996_dfs_init_radar_specs(struct mt7996_phy *phy)
3021 struct mt7996_dev *dev = phy->dev;
3024 switch (dev->mt76.region) {
3038 return -EINVAL;
3041 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
3043 &radar_specs->radar_pattern[i]);
3048 return mt7996_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
3051 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy)
3053 struct mt7996_dev *dev = phy->dev;
3055 int err, rdd_idx = mt7996_get_rdd_idx(phy, false);
3057 prev_state = phy->mt76->dfs_state;
3058 dfs_state = mt76_phy_dfs_state(phy->mt76);
3064 mt7996_dfs_stop_radar_detector(phy);
3070 err = mt7996_dfs_init_radar_specs(phy);
3074 err = mt7996_dfs_start_radar_detector(phy);
3078 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
3086 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
3090 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
3098 mt7996_dfs_stop_radar_detector(phy);
3099 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
3115 u32 duration = flow->duration << 8;
3118 iter = list_first_entry_or_null(&dev->twt_list,
3120 if (!iter || !iter->sched || iter->start_tsf > duration) {
3122 list_add(&flow->list, &dev->twt_list);
3126 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) {
3127 start_tsf = iter->start_tsf +
3128 mt7996_mac_twt_duration_align(iter->duration);
3129 if (list_is_last(&iter->list, &dev->twt_list))
3132 if (!iter_next->sched ||
3133 iter_next->start_tsf > start_tsf + duration) {
3134 list_add(&flow->list, &iter->list);
3140 list_add_tail(&flow->list, &dev->twt_list);
3153 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST)
3154 return -EOPNOTSUPP;
3157 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT)
3158 return -EOPNOTSUPP;
3160 twt_agrt = (struct ieee80211_twt_params *)twt->params;
3163 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT)))
3164 return -EOPNOTSUPP;
3167 le16_to_cpu(twt_agrt->req_type));
3168 mantissa = le16_to_cpu(twt_agrt->mantissa);
3169 duration = twt_agrt->min_twt_dur << 8;
3173 return -EOPNOTSUPP;
3182 u16 type = le16_to_cpu(twt_agrt->req_type);
3190 if (!(msta_link->twt.flowid_mask & BIT(i)))
3193 f = &msta_link->twt.flow[i];
3194 if (f->duration == twt_agrt->min_twt_dur &&
3195 f->mantissa == twt_agrt->mantissa &&
3196 f->exp == exp &&
3197 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) &&
3198 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) &&
3199 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER))
3211 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv;
3212 struct ieee80211_twt_params *twt_agrt = (void *)twt->params;
3213 struct mt7996_sta_link *msta_link = &msta->deflink;
3214 u16 req_type = le16_to_cpu(twt_agrt->req_type);
3223 mutex_lock(&dev->mt76.mutex);
3225 if (dev->twt.n_agrt == MT7996_MAX_TWT_AGRT)
3228 if (hweight8(msta_link->twt.flowid_mask) ==
3229 ARRAY_SIZE(msta_link->twt.flow))
3232 if (twt_agrt->min_twt_dur < MT7996_MIN_TWT_DUR) {
3234 twt_agrt->min_twt_dur = MT7996_MIN_TWT_DUR;
3241 flowid = ffs(~msta_link->twt.flowid_mask) - 1;
3242 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID);
3243 twt_agrt->req_type |= le16_encode_bits(flowid,
3246 table_id = ffs(~dev->twt.table_mask) - 1;
3250 flow = &msta_link->twt.flow[flowid];
3252 INIT_LIST_HEAD(&flow->list);
3253 flow->wcid = msta_link->wcid.idx;
3254 flow->table_id = table_id;
3255 flow->id = flowid;
3256 flow->duration = twt_agrt->min_twt_dur;
3257 flow->mantissa = twt_agrt->mantissa;
3258 flow->exp = exp;
3259 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION);
3260 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE);
3261 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER);
3265 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp;
3269 flow->sched = true;
3270 flow->start_tsf = mt7996_mac_twt_sched_list_add(dev, flow);
3271 curr_tsf = __mt7996_get_tsf(hw, &msta->vif->deflink);
3272 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem);
3273 flow_tsf = curr_tsf + interval - rem;
3274 twt_agrt->twt = cpu_to_le64(flow_tsf);
3276 list_add_tail(&flow->list, &dev->twt_list);
3278 flow->tsf = le64_to_cpu(twt_agrt->twt);
3280 if (mt7996_mcu_twt_agrt_update(dev, &msta->vif->deflink, flow,
3285 dev->twt.table_mask |= BIT(table_id);
3286 msta_link->twt.flowid_mask |= BIT(flowid);
3287 dev->twt.n_agrt++;
3290 mutex_unlock(&dev->mt76.mutex);
3292 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD);
3293 twt_agrt->req_type |=
3295 twt->control = twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED;
3305 lockdep_assert_held(&dev->mt76.mutex);
3307 if (flowid >= ARRAY_SIZE(msta_link->twt.flow))
3310 if (!(msta_link->twt.flowid_mask & BIT(flowid)))
3313 flow = &msta_link->twt.flow[flowid];
3317 list_del_init(&flow->list);
3318 msta_link->twt.flowid_mask &= ~BIT(flowid);
3319 dev->twt.table_mask &= ~BIT(flow->table_id);
3320 dev->twt.n_agrt--;