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/linux/arch/x86/include/asm/fpu/
H A Dxstate.h49 /* Supervisor features which are enabled only in guest FPUs */
52 /* All currently supported supervisor features */
58 * A supervisor state component may not always contain valuable information,
59 * and its size may be huge. Saving/restoring such supervisor state components
61 * be avoided. Such supervisor state components should only be saved/restored
62 * on demand. The on-demand supervisor features are set in this mask.
64 * Unlike the existing supported supervisor features, an independent supervisor
66 * supervisor state component cannot be saved/restored at each context switch.
68 * To support an independent supervisor feature, a developer should follow the
70 * - Do dynamically allocate a buffer for the supervisor state component.
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/linux/arch/m68k/ifpsp060/
H A Dos.S58 | or supervisor application space. The examples below use simple "move"
59 | instructions for supervisor mode applications and call _copyin()/_copyout()
76 | Writes to data memory while in supervisor mode.
79 | a0 - supervisor source address
82 | 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
89 btst #0x5,0x4(%a6) | check for supervisor state
107 | Reads from data/instruction memory while in supervisor mode.
111 | a1 - supervisor destination address
113 | 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
122 btst #0x5,0x4(%a6) | check for supervisor state
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H A DCHANGES91 bit 18:16 = x10 (TM; x = 1 for supervisor mode)
113 bit 18:16 = x01 (TM; x = 1 for supervisor mode)
H A Diskeleton.S72 btst #0x5,%sp@ | supervisor bit set in saved SR?
192 | d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
258 | d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
25 All RISC-V systems that conform to the supervisor ISA specification are
50 The interrupt sources are defined by the RISC-V supervisor ISA manual,
52 supervisor mode:
53 - Source 1 is the supervisor software interrupt, which can be sent by
55 - Source 5 is the supervisor timer interrupt, which can be configured
57 - Source 9 is the supervisor external interrupt, which chains to all
/linux/arch/m68k/fpsp040/
H A Dskeleton.S377 btst #0x5,%sp@ | supervisor bit set in saved SR?
387 | mem_write --- write to user or supervisor address space
389 | Writes to memory while in supervisor mode. copyout accomplishes
393 | a0 - supervisor source address
397 | The supervisor source address is guaranteed to point into the supervisor
404 | If the EXC_SR shows that the exception was from supervisor space,
406 | there shouldn't be any supervisor mode floating point exceptions.
410 btstb #5,EXC_SR(%a6) |check for supervisor state
427 | mem_read --- read from user or supervisor address space
429 | Reads from memory while in supervisor mode. copyin accomplishes
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H A Dx_store.S167 exg %a0,%a1 |a0=supervisor source, a1=user dest
231 exg %a0,%a1 |a0=supervisor source, a1=user dest
251 exg %a0,%a1 |a0=supervisor source, a1=user dest
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml179 The standard Smaia supervisor-level extension for the advanced
187 to delegate the hpmcounters to supervisor mode so that they are
188 directly accessible in the supervisor mode as ratified in the
225 The standard Ssaia supervisor-level extension for the advanced
226 interrupt architecture for supervisor-mode-visible csr and
232 The standard Ssccfg supervisor-level extension for configuring
233 the delegated hpmcounters to be accessible directly in supervisor
247 The standard Sscofpmf supervisor-level extension for count overflow
260 The standard Sscsrind supervisor-level extension extends the
280 The standard Ssstateen extension for supervisor-mode view of the
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/linux/arch/microblaze/include/asm/
H A Dmmu.h36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor read, User read */
44 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
/linux/Documentation/hwmon/
H A Dsl28cpld.rst21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
H A Dpli1209bc.rst8 * Digital Supervisor PLI1209BC
22 The Vicor PLI1209BC is an isolated digital power system supervisor that provides
/linux/Documentation/arch/x86/x86_64/
H A Dfred.rst20 establishes the full supervisor context and that event return
53 Full supervisor/user context
56 FRED event delivery atomically save and restore full supervisor/user
/linux/arch/m68k/include/asm/
H A Dmcfdma.h89 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
90 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
101 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
102 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
H A Dm54xxacr.h36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
96 * cacheable and supervisor access only.
H A Dmcfmmu.h60 #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
79 #define MMUDR_SP 0x00000020 /* Supervisor access enable */
/linux/arch/sparc/include/asm/
H A Dpcr.h20 #define PCR_STRACE 0x00000002 /* Trace supervisor events */
39 #define PCR_N4_STRACE 0x00000008 /* Trace supervisor events */
H A Diommu_32.h63 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
77 #define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
/linux/drivers/reset/
H A Dreset-tps380x.c3 * TI TPS380x Supply Voltage Supervisor and Reset Controller Driver
125 MODULE_DESCRIPTION("TI TPS380x Supply Voltage Supervisor and Reset Driver");
/linux/Documentation/translations/zh_CN/core-api/
H A Derrseq.rst77 struct supervisor {
82 struct supervisor su;
/linux/Documentation/arch/riscv/
H A Duabi.rst31 #. Standard supervisor-level extensions (starting with 'S') will be listed
32 after standard unprivileged extensions. If multiple supervisor-level
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
517 #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
/linux/arch/mips/include/asm/octeon/
H A Docteon.h221 /* R/W If set (and SX set), supervisor-level
228 /* R/W If set (and SX set), supervisor-level
269 * supervisor mode. */
/linux/arch/nios2/mm/
H A Dfault.c32 #define EXC_SUPERV_INSN_ACCESS 9 /* Supervisor only instruction address */
33 #define EXC_SUPERV_DATA_ACCESS 11 /* Supervisor only data address */
/linux/Documentation/virt/kvm/x86/
H A Dhypercalls.rst82 shared page that contains parts of supervisor visible register state.
83 The guest can map this shared page to access its supervisor register
/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h550 #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
551 #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
585 #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
602 #define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */
603 #define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */
604 #define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */
605 #define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */
606 #define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */
607 #define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */
608 #define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */

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