| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | intel,stratix10-soc-fpga-mgr.yaml | 4 $id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml#
7 title: Intel Stratix10 SoC FPGA Manager
15 The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard
16 processor system (HPS) and a Secure Device Manager (SDM). The Stratix10
18 on the die.The driver communicates with SDM/ATF via the stratix10-svc
24 - intel,stratix10-soc-fpga-mgr
35 compatible = "intel,stratix10-soc-fpga-mgr";
|
| H A D | intel-stratix10-soc-fpga-mgr.txt | 1 Intel Stratix10 SoC FPGA Manager
7 - compatible : should contain "intel,stratix10-soc-fpga-mgr" or
15 compatible = "intel,stratix10-soc-fpga-mgr";
|
| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | intel,stratix10-svc.yaml | 4 $id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml#
7 title: Intel Service Layer Driver for Stratix10 SoC
14 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
26 Intel Stratix10 service layer driver, running at privileged exception level
35 - intel,stratix10-svc
58 $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
84 compatible = "intel,stratix10-svc";
89 compatible = "intel,stratix10-soc-fpga-mgr";
|
| H A D | intel,stratix10-svc.txt | 1 Intel Service Layer Driver for Stratix10 SoC
3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
15 Intel Stratix10 service layer driver, running at privileged exception level
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
53 compatible = "intel,stratix10-svc";
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | intel,stratix10.yaml | 4 $id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
7 title: Intel SoCFPGA Stratix10 platform clock controller
14 const: intel,stratix10-clkmgr
32 compatible = "intel,stratix10-clkmgr";
|
| H A D | intc_stratix10.txt | 1 Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
9 "intel,stratix10-clkmgr"
17 compatible = "intel,stratix10-clkmgr";
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | altera.yaml | 58 - altr,socfpga-stratix10-socdk
59 - altr,socfpga-stratix10-swvp
60 - const: altr,socfpga-stratix10
|
| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | socfpga-reset.txt | 5 "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
|
| H A D | altr,rst-mgr.yaml | 17 - description: Stratix10 ARM64 SoC
19 - const: altr,stratix10-rst-mgr
41 const: altr,stratix10-rst-mgr
|
| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 235 Stratix10 SoCFPGA ECC Manager (ARM64)
236 The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
237 in a shared register similar to the Arria10. However, Stratix10 ECC
240 that only 1 interrupt is sent in Stratix10 because the double bit errors
245 - altr,sysgr-syscon : phandle to Stratix10 System Manager Block
|
| H A D | altr,socfpga-ecc-manager.yaml | 15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
47 description: phandle to Stratix10 System Manager Block with the ECC manager registers
|
| /freebsd/sys/contrib/device-tree/src/arm64/altera/ |
| H A D | socfpga_stratix10_swvp.dts | 10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
|
| H A D | socfpga_stratix10.dtsi | 9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
74 compatible = "intel,stratix10-svc";
79 compatible = "intel,stratix10-soc-fpga-mgr";
169 compatible = "intel,stratix10-clkmgr";
401 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
|
| H A D | socfpga_stratix10_socdk_nand.dts | 10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
|
| H A D | socfpga_stratix10_socdk.dts | 10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | socfpga-dwmac.txt | 10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
17 on the Arria10/Stratix10/Agilex platforms, the register shift represents
|
| H A D | altr,socfpga-stmmac.yaml | 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
127 bits, while on the Arria10/Stratix10/Agilex platforms, the
|
| /freebsd/sys/arm64/intel/ |
| H A D | stratix10-svc.c | 59 #include <arm64/intel/stratix10-svc.h>
177 vmem = vmem_create("stratix10 vmem", 0, 0, PAGE_SIZE, in s10_get_memory()
221 if (!ofw_bus_is_compatible(dev, "intel,stratix10-svc")) in s10_svc_probe()
|
| H A D | stratix10-soc-fpga-mgr.c | 57 #include <arm64/intel/stratix10-svc.h>
245 if (!ofw_bus_is_compatible(dev, "intel,stratix10-soc-fpga-mgr")) in fpgamgr_s10_probe()
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/altera/ |
| H A D | socfpga-system.txt | 15 ARM64 - Stratix10
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/altera/ |
| H A D | altr,sys-mgr.yaml | 17 - description: Stratix10 SoC
|
| /freebsd/sys/dev/mmc/host/ |
| H A D | dwmmc_altera.c | 77 if (ofw_bus_node_is_compatible(root, "altr,socfpga-stratix10")) { in altera_dwmmc_attach()
|
| /freebsd/sys/dev/dwc/ |
| H A D | if_dwc_socfpga.c | 84 if (ofw_bus_node_is_compatible(root, "altr,socfpga-stratix10")) in if_dwc_socfpga_mii_clk()
|
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | altr,pcie-root-port.yaml | 17 family of chips. The Stratix10 family of chips is supported by the
|
| /freebsd/sys/contrib/device-tree/src/arm64/intel/ |
| H A D | socfpga_agilex5.dtsi | 321 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
|