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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
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/linux/drivers/net/dsa/
H A Dvitesse-vsc73xx-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
20 #include "vitesse-vsc73xx.h"
25 #define VSC73XX_CMD_SPI_BLOCK_SHIFT 5
30 * struct vsc73xx_spi - VSC73xx SPI state container
55 struct vsc73xx_spi *vsc_spi = vsc->priv; in vsc73xx_spi_read()
63 return -EINVAL; in vsc73xx_spi_read()
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H A Dvitesse-vsc73xx-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
8 * These switches have a built-in 8051 CPU and can download and execute a
10 * handling the switch in a memory-mapped manner by connecting to that external
34 #include "vitesse-vsc73xx.h"
36 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */
40 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Subblocks 0-4, 6, 7 */
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/linux/Documentation/hwmon/
H A Dsparx5-temp.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 Microchip SparX-5 SoC
10 Prefix: 'sparx5-temp'
12 Addresses scanned: -
19 -----------
24 The sensor has a range of -40°C to +125°C and an accuracy of +/-5°C.
27 -------------
/linux/Documentation/devicetree/bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
30 * (1/1000000)/((2^-59)/X) in sparx5_ptp_get_1ppm()
35 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
60 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
85 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set()
93 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_ptp_hwtstamp_set()
94 return -EINVAL; in sparx5_ptp_hwtstamp_set()
96 switch (cfg->tx_type) { in sparx5_ptp_hwtstamp_set()
98 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; in sparx5_ptp_hwtstamp_set()
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H A Dsparx5_main.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
135 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */
136 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */
137 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */
153 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */
154 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */
180 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */
181 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */
217 switch (sparx5->target_ct) { in is_sparx5()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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