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/freebsd/sys/contrib/device-tree/Bindings/power/supply/
H A Dmax17040_battery.txt5 - compatible : "maxim,max17040", "maxim,max17041", "maxim,max17043",
7 "maxim,max17058", "maxim,max17059" or "maxim,max77836-battery"
8 - reg: i2c slave address
11 - maxim,alert-low-soc-level : The alert threshold that sets the state of
12 charge level (%) where an interrupt is
16 - maxim,double-soc : Certain devices return double the capacity.
19 SOC == State of Charge == Capacity.
20 - maxim,rcomp : A value to compensate readings for various
25 - interrupts : Interrupt line see Documentation/devicetree/
26 bindings/interrupt-controller/interrupts.txt
[all …]
H A Dda9150-fg.txt1 Dialog Semiconductor DA9150 Fuel-Gauge Power Supply bindings
4 - compatible: "dlg,da9150-fuel-gauge" for DA9150 Fuel-Gauge Power Supply
7 - dlg,update-interval: Interval time (milliseconds) between battery level checks.
8 - dlg,warn-soc-level: Battery discharge level (%) where warning event raised.
9 [1 - 100]
10 - dlg,crit-soc-level: Battery discharge level (%) where critical event raised.
11 This value should be lower than the warning level.
12 [1 - 100]
17 fuel-gauge {
18 compatible = "dlg,da9150-fuel-gauge";
[all …]
H A Dmaxim,max17040.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-suppl
[all...]
H A Ddlg,da9150-fuel-gauge.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/dlg,da9150-fuel-gauge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA9150 Fuel-Gauge Power Supply
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
17 const: dlg,da9150-fuel-gauge
19 dlg,update-interval:
21 description: Interval time (milliseconds) between battery level checks.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsprd,pinctrl.txt8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
13 have several systems (AP/CP/CM4) on one SoC.).
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
35 - input-enable
36 - input-disable
37 - outpu
[all...]
H A Drenesas,rzn1-pinctrl.txt1 Renesas RZ/N1 SoC Pinctrl node description.
4 -------------------
6 - compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
7 followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
9 "renesas,r9a06g032-pinctrl" for RZ/N1D
10 "renesas,r9a06g033-pinctrl" for RZ/N1S
11 - reg: Address base and length of the memory area where the pin controller
13 - clocks: phandle for the clock, see the description of clock-names below.
14 - clock-names: Contains the name of the clock:
18 pinctrl: pin-controller@40067000 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpc5121-psc.txt4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
[all …]
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
18 chip? For the MPC5200; the answer is easy. Most of the SoC devices
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
[all …]
H A Dmpic.txt14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,idle-state.txt3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
41 back into Elevation Level (EL) which trampolines the control back to the
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
53 of this low power mode would be considered high even though at a cpu level,
55 with the Resource power manager (RPM) processor in the SoC to indicate a
[all …]
H A Dqcom,llcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
16 SoC, the idea is to minimize the local caches at the clients and migrate to
24 - qcom,sc7180-llcc
25 - qcom,sc7280-llcc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
23 - qcom,ipq9574-qusb2-phy
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Dicx-metrics.json3 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
4 … 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR…
9 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
10 …- INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) …
39 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
45 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
51 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
57 "BriefDescription": "The ratio of Executed- by Issued-Uops",
61 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
64 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt104xsi-pre.dtsi2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2013-2014 Freescale Semiconductor Inc.
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
[all …]
H A Dp4080si-pre.dtsi2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
[all …]
H A Dp2041si-pre.dtsi2 * P2041 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
86 #address-cells = <1>;
87 #size-cells = <0>;
93 next-level-cache = <&L2_0>;
[all …]
H A Dp3041si-pre.dtsi2 * P3041 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
87 #address-cells = <1>;
88 #size-cells = <0>;
94 next-level-cache = <&L2_0>;
[all …]
H A Dp5040si-pre.dtsi2 * P5040 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
99 #address-cells = <1>;
100 #size-cells = <0>;
106 next-level-cache = <&L2_0>;
[all …]
H A Dt102xsi-pre.dtsi2 * T1024/T1023 Silicon/SoC Device Tree Source (pre include)
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>;
[all …]
H A Db4860si-pre.dtsi2 * B4860 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
72 #address-cells = <1>;
73 #size-cells = <0>;
79 next-level-cache = <&L2_1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC cluster cpufreq device
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Apple T6002 "M1 Ultra" SoC
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
[all …]

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