Lines Matching +full:soc +full:- +full:level
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
41 back into Elevation Level (EL) which trampolines the control back to the
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
53 of this low power mode would be considered high even though at a cpu level,
55 with the Resource power manager (RPM) processor in the SoC to indicate a
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
61 The devicetree representation of the idle state should be -
65 - compatible: Must be one of -
66 "qcom,idle-state-ret",
67 "qcom,idle-state-spc",
68 "qcom,idle-state-pc",
69 and "arm,idle-state".
75 idle-states {
77 compatible = "qcom,idle-state-spc", "arm,idle-state";
78 entry-latency-us = <150>;
79 exit-latency-us = <200>;
80 min-residency-us = <2000>;
84 [1]. Documentation/devicetree/bindings/cpu/idle-states.yaml