Single\-Core (full) in projects: freebsd

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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A D	ti,c64x+megamod-pic.txt	`2 ------------------- 4 * C64X+ Core Interrupt Controller 6 The core interrupt controller provides 16 prioritized interrupts to the 7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively. 8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt 9 sources coming from outside the core. 12 -------------------- 13 - compatible: Should be "ti,c64x+core-pic"; 14 - #interrupt-cells: <1> 17 ------------------------------ [all …]`
H A D	apple,aic2.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Hector Martin <marcan@marcan.st> 18 - Level-triggered hardware IRQs wired to SoC blocks 19 - Single mask bit per IRQ 20 - Automatic masking on event delivery (auto-ack) 21 - Software triggering (ORed with hw line) 22 - Automatic prioritization (single event/ack register per CPU, lower IRQs = [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A D	ctrl.txt	`11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml 15 - compatible: Must be one of: 16 "ti,am3-scm" 17 "ti,am4-scm" 18 "ti,dm814-scrm" 19 "ti,dm816-scrm" 20 "ti,omap2-scm" 21 "ti,omap3-scm" 22 "ti,omap4-sc [all...]`
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2… 108 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2… 111 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config… 114 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config… 117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 123 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 126 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 129 …ta cache entering write streaming mode.This event counts for each entry into write-streaming mode", 132 …ata cache entering write streaming mode.This event counts for each entry into write-streaming mode" [all …]
/freebsd/sys/contrib/device-tree/Bindings/
H A D	example-schema.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 # All the top-level keys are standard json-schema keywords except for 10 $id: http://devicetree.org/schemas/example-schema.yaml# 11 # $schema is the meta-schema this schema should be validated with. 12 $schema: http://devicetree.org/meta-schemas/core.yaml# 17 - Rob Herring <robh@kernel.org> 20 A more detailed multi-line description of the binding. 44 - items: 51 - enum: [all …]`
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A D	st,stm32-adc.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 STM32 ADC is a successive approximation analog-to-digital converter. 12 in single, continuous, scan or discontinuous mode. Result of the ADC is 13 stored in a left-aligned or right-aligned 32-bit data register. 17 voltage goes beyond the user-defined, higher or lower thresholds. 22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 27 - st,stm32f4-adc-core [all …]
H A D	xilinx-xadc.txt	16 communication. Xilinx provides a standard IP core that can be used to access the 17 System Monitor through an AXI interface in the FPGA fabric. This IP core is 22 - compatible: Should be one of 23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device 25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to 27 * "xlnx,system-management-wiz-1.3": When using the 28 Xilinx System Management Wizard fabric IP core to access the 30 - reg: Address and length of the register set for the device 31 - interrupts: Interrupt for the XADC control interface. 32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A D	cache.json	102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami… 117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami… 126 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami… 129 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami… 132 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami… 135 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami… 138 …el cache write streaming mode. This event counts for each cycle where the core is in write streami… 141 …el cache write streaming mode. This event counts for each cycle where the core is in write streami… [all …]
/freebsd/stand/lua/
H A D	menu.lua.8	2 .\" SPDX-License-Identifier: BSD-2-Clause 36 It also contains definitions for the built-in menus, some of which are 58 key is itself a table, then each value in this table defines a single entry in 66 This function must return a table, each value of which defines a single entry 72 .Bl -tag -width disable-module_module -offset indent 96 .Ic core.MENU_SEPARATOR 102 A table of case-sensitive aliases for this menu entry. 112 .Ic core.MENU_SEPARATOR . 115 .Xr core.lua 8 . 117 .Bl -tag -width core.MENU_CAROUSEL_ENTRY -offset indent [all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A D	pistachio-clock.txt	`4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral 6 from the device-tree. 9 ---------------- 12 defined with the following clock-output-names: 13 - "xtal": External 52Mhz oscillator (required) 14 - "audio_clk_in": Alternate audio reference clock (optional) 15 - "enet_clk_in": Alternate ethernet PHY clock (optional) 17 Core clock controller: 18 ---------------------- 20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT [all …]`
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A D	ti,k3-r5f-rproc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5 [all...]`
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	other.json	3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 9 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc… 15 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 21 …Core cycles where the core was running with power-delivery for license level 1. This includes hig… 27 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 33 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl… 45 …core's cache, after the data is forwarded back to the requestor and indicating the data was found … 57 …core's caches, after the data is forwarded back to the requestor, and indicating the data was foun… 69 …core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Ex… 81 … was not found (IHitI) in this core's caches. A single snoop response from the core counts on all … [all …]
/freebsd/lib/libpmc/
H A D	pmc.core.3	`28 .Nm pmc.core 31 .Tn Core Solo 33 .Tn Core Duo 41 .Tn "Core Solo" 43 .Tn "Core Duo" 50 .%B IA-32 Intel\(rg Architecture Software Developer's Manual 52 .%N Order Number 253669-027US 63 .Bl -column "PMC_CAP_INTERRUPT" "Support" 80 .Bl -tag -width indent 86 Configure the PMC to count the number of de-asserted to asserted [all …]`
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	cache.json	111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 117 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config… 120 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config… 123 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2… 126 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2… 141 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 144 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 147 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 150 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… [all …]
/freebsd/usr.bin/netstat/
H A D	netstat.1	`35 .Bk -words 36 .Bl -tag -width "netstat" 39 .Op Fl -libxo 44 .Op Fl -libxo 47 .Op Fl M Ar core 51 .Op Fl -libxo 54 .Op Fl M Ar core 59 .Op Fl -libxo 62 .Op Fl M Ar core [all...]`
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A D	cpu-topology.txt	`6 1 - Introduction 12 - socket 13 - cluster 14 - core 15 - thread 17 The bottom hierarchy level sits at core or thread level depending on whether 18 symmetric multi-threading (SMT) is supported or not. 23 in the system and map to the hierarchy level "core" above. 29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be 39 2 - cpu-map node [all …]`
/freebsd/contrib/llvm-project/lldb/source/Plugins/Trace/intel-pt/
H A D	LibiptDecoder.h	1 //===-- LibiptDecoder.h --======---------------------------------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 14 #include "forward-declarations.h" 15 #include "intel-pt.h" 54 /// Decode a raw Intel PT trace for a single thread given in \p buffer and 64 /// Decode a raw Intel PT trace for a single thread that was collected in a per 65 /// cpu core basis. 76 /// A map from cpu core id to raw intel pt buffers. 81 /// determine in which core a certain part of the execution ocurred. [all …]
/freebsd/contrib/ntp/html/
H A D	orphan.html	1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> 4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1"> 12 <!-- #BeginDate format:En2m -->4-Aug-2011 23:40<!-- #EndDate --> 16 … single-point failures and multiple server redundancy is not possible. Orphan mode is intended to… 17 …core servers operating at the lowest stratum. Good practice is to configure each of these servers … 18 … available to any core server, one of them can provide a simulated UTC source for all other hosts … 25 address of each core server. Each orphan child chooses the orphan 26 parent as the core server with the smallest metric.</p> 27 …p>For orphan mode to work well, each core server with available sources should operate at the same… 31 …o discipline the system clock using the other servers as backup. Only the core servers and orphan … [all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A D	i2c.txt	`8 ----------------------------- 10 - #address-cells - should be <1>. Read more about addresses below. 11 - #size-cells - should be <0>. 12 - compatible - name of I2C bus controller 18 are described by a single value. 21 ----------------------------- 26 - clock-frequency 29 - i2c-bus 31 devices and non-I2C devices, the 'i2c-bus' subnode can be used for 32 populating I2C devices. If the 'i2c-bus' subnode is present, only [all …]`
/freebsd/share/doc/smm/03.fsck/
H A D	2.t	38 .I "super-block" . 39 The super-block is built when the file system is created (\c 42 The super-block 46 Because the super-block contains critical data, 56 or other hard disk error causes the default super-block 74 the range 5-13. 80 a doubly indirect block contains 1024 addresses of further single indirect 91 The block size of the file system is maintained in the super-block, 130 A single hardware failure that destroyed the top platter 131 could cause the loss of all copies of the redundant super-blocks. [all …]
/freebsd/share/doc/smm/18.net/
H A D	5.t	35 A single mechanism is used for data storage: memory buffers, or 45 struct mbuf m_act; / link in higher-level mbuf list / 50 accumulated. By convention, the mbufs common to a single object 62 #define mtod(\fIx\fP,\fIt\fP) ((\fIt\fP)((int)(\fIx\fP) + (\fIx\fP)->m_off)) 77 so that copies of pages may be made without core to core 109 each free a single mbuf, \fIm\fP, and any associated external storage area, 122 of core to core copies. The original mbuf chain must have at 133 bytes. If \fIdiff\fP is non-negative, \fIdiff\fP bytes 158 may be ``pulled up'' with a single \fIm_pullup\fP call. 172 #define dtom(x) ((struct mbuf )((int)x & ~(MSIZE-1)))
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A D	ite,it66121.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Phong LE <ple@baylibre.com> 11 - Neil Armstrong <neil.armstrong@linaro.org> 14 The IT66121 is a high-performance and low-power single channel HDMI 21 - ite,it66121 22 - ite,it6610 27 reset-gpios: 31 vrf12-supply: [all …]`
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A D	baikal,bt1-pcie.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Baikal-T1 PCIe Root Port Controller 10 - Serge Semin <fancer.lancer@gmail.com> 13 Embedded into Baikal-T1 SoC Root Complex controller with a single port 14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured 15 to have just a single Root Port function and is capable of establishing the 18 performed by software. There four in- and four outbound iATU regions [all …]
/freebsd/sys/contrib/device-tree/Bindings/spmi/
H A D	qcom,spmi-pmic-arb.txt	4 controller with wrapping arbitration logic to allow for multiple on-chip 5 devices to control a single SPMI master. 13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for 17 - compatible : should be "qcom,spmi-pmic-arb". 18 - reg-names : must contain: 19 "core" - core registers 20 "intr" - interrupt controller registers 21 "cnfg" - configuration registers 23 "chnls" - tx-channel per virtual slave registers. 24 "obsrvr" - rx-channel (called observer) per virtual slave registers. [all …]
/freebsd/lib/libpmc/pmu-events/
H A D	README	9 tree tools/perf/pmu-events/arch/foo. 11 - Regular files with '.json' extension in the name are assumed to be 14 - The CSV file that maps a specific CPU to its set of PMU events is to 17 - Directories are traversed, but all other files are ignored. 19 - To reduce JSON event duplication per architecture, platform JSONs may 26 such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic 27 should be placed in a separate JSON file - where the file name identifies 28 the topic. Eg: "Floating-point.json". 33 $ ls tools/perf/pmu-events/arch/x86/Silvermont_core 34 Cache.json Memory.json Virtual-Memory.json [all …]

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