Lines Matching +full:single +full:- +full:core

28 .Nm pmc.core
31 .Tn Core Solo
33 .Tn Core Duo
41 .Tn "Core Solo"
43 .Tn "Core Duo"
50 .%B IA-32 Intel\(rg Architecture Software Developer's Manual
52 .%N Order Number 253669-027US
63 .Bl -column "PMC_CAP_INTERRUPT" "Support"
80 .Bl -tag -width indent
86 Configure the PMC to count the number of de-asserted to asserted
112 Events that require core-specificity to be specified use a
114 .Dq Li core= Ns Ar value ,
118 .Bl -tag -width indent -compact
122 Measure event conditions on this core.
133 .Bl -tag -width indent -compact
148 .Bl -tag -width "exclude" -compact
165 .Bl -tag -width indent -compact
182 Core PMCs support the following events:
183 .Bl -tag -width indent
271 .It Li Bus_Locks_Clocks Op ,core= Ns Ar core
274 .It Li Bus_Not_In_Use Op ,core= Ns Ar core
276 The number of cycles when there is no transaction from the core.
279 .Op ,core= Ns Ar core
297 .It Li Bus_Trans_Brd Op ,core= Ns Ar core
304 .It Li Bus_Trans_Def Op ,core= Ns Ar core
309 .Op ,core= Ns Ar core
316 .Op ,core= Ns Ar core
322 .Op ,core= Ns Ar core
331 .Op ,core= Ns Ar core
337 .Op ,core= Ns Ar core
343 .Op ,core= Ns Ar core
346 The number of completed read-for-ownership transactions.
349 The number of completed write-back transactions from the data cache
350 unit, excluding L2 write-backs.
362 .It Li DCU_Snoop_To_Share Op ,core= Ns core
394 un-cacheable.
395 .It Li Dbus_Busy Op ,core= Ns Ar core
397 The number of core cycles during which the data bus was busy.
398 .It Li Dbus_Busy_Rd Op ,core= Ns Ar core
401 data to a core.
419 .Bl -tag -width indent -compact
461 streaming buffers counting both cacheable and un-cacheable fetches.
483 .It Li L2_ADS Op ,core= Ns core
488 .Op ,core= Ns Ar core
495 .Op ,core= Ns Ar core
500 .Op ,core= Ns Ar core
506 .Op ,core= Ns Ar core
511 .It Li L2_M_Lines_In Op ,core= Ns Ar core
515 .Op ,core= Ns Ar core
522 .Op ,core= Ns Ar core
529 .Op ,core= Ns Ar core
536 .Op ,core= Ns Ar core
543 .Op ,core= Ns Ar core
589 The number of non-halted bus cycles.
619 The number of SSE/SSE2 packed single precision compute instructions
623 The number of SSE/SSE2 scalar single precision instructions retired,
627 The number of SSE/SSE2 scalar single precision instructions retired.
630 The number of SSE/SSE2 single precision compute instructions retired.
633 The number of SSE2 128-bit integer instructions retired.
657 The number of times self-modifying code was detected.
699 The number of non-halted bus cycles of this code while the other core
703 The duration in a thermal trip based on the current core clock.
709 The number of core clock cycles when the clock signal on a specific
710 core is not halted.
714 The number of micro-ops retired.
717 The following table shows the mapping between the PMC-independent
721 .Bl -column "branch-mispredicts" "Description"
724 .It Li branch-mispredicts Ta Li Br_MisPred_Ret
725 .It Li dc-misses Ta (unsupported)
726 .It Li ic-misses Ta Li ICache_Misses
729 .It Li unhalted-cycles Ta (unsupported)
738 .%N Order Number 309222-017
742 .Bl -tag -width indent -compact
745 on a single core.