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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h38 * SerDes HAL driver API
39 * @ingroup group_serdes SerDes
44 * @brief Header file for the SerDes HAL driver
65 /* Relevant to Serdes hssp and 25g */
68 /* Relevant to Serdes hssp only */
71 /* Relevant to Serdes hssp and 25g */
73 /* Relevant to Serdes hssp only */
75 /* Relevant to Serdes 25g only */
79 /* Relevant to Serdes hssp only */
95 /** Serdes loopback mode */
[all …]
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_regs.h58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
79 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_hssp.h38 * SerDes HAL driver API
39 * @ingroup group_serdes SerDes
44 * @brief Header file for the SerDes HAL driver
62 * Initializes a SERDES group object
65 * The SERDES register file base pointer
86 /** @} end of SERDES group */
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-am654-serdes.yaml4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
19 - ti,phy-am654-serdes
26 - const: serdes
41 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
43 ti,serdes-clk:
44 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
52 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
56 - description: Clock output names for SERDES 0
[all …]
H A Dphy-ocelot-serdes.txt1 Microsemi Ocelot SerDes muxing driver
5 space for setting up the SerDes to switch port muxing.
7 A SerDes X can be "muxed" to work with switch port Y or Z for example.
8 One specific SerDes can also be used as a PCIe interface.
10 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
12 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
24 - compatible: should be "mscc,vsc7514-serdes"
27 SerDes macro. The second defines the macro to use. They are
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
32 serdes: serdes {
[all …]
H A Dmscc,vsc7514-serdes.yaml4 $id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
7 title: Microsemi Ocelot SerDes muxing
15 space for setting up the SerDes to switch port muxing.
17 A SerDes X can be "muxed" to work with switch port Y or Z for example.
18 One specific SerDes can also be used as a PCIe interface.
20 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
22 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
35 - mscc,vsc7514-serdes
40 The first number defines the input port to use for a given SerDes macro.
42 dt-bindings/phy/phy-ocelot-serdes.h
[all …]
H A Dmicrochip,sparx5-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
7 title: Microchip Sparx5 Serdes controller
13 The Sparx5 SERDES interfaces share the same basic functionality, but
16 The following list lists the SERDES features:
31 The SERDES6G is a high-speed SERDES interface, which can operate at
41 The SERDES10G is a high-speed SERDES interface, which can operate at
54 The SERDES25G is a high-speed SERDES interface, which can operate at
67 pattern: "^serdes@[0-9a-f]+$"
70 const: microchip,sparx5-serdes
78 - The main serdes input port
[all …]
H A Dmicrochip,lan966x-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
7 title: Microchip Lan966x Serdes controller
16 interfaces. The Serdes controller will allow to configure these interfaces
23 interface SerDes 2.
27 pattern: "^serdes@[0-9a-f]+$"
30 const: microchip,lan966x-serdes
42 dt-bindings/phy/phy-lan966x-serdes.
53 serdes: serdes@e2004010 {
54 compatible = "microchip,lan966x-serdes";
H A Dti,phy-am654-serdes.txt1 TI AM654 SERDES
4 - compatible: Should be "ti,phy-am654-serdes"
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
21 - clocks: List of clock-specifiers representing the input to the SERDES.
25 SERDES. Should have 3 items for CMU reference clock,
34 The following macros are defined in dt-bindings/phy/phy-am654-serdes.h
36 specifying the clocks created by SERDES.
60 serdes0: serdes@900000 {
61 compatible = "ti,phy-am654-serdes";
63 reg-names = "serdes";
[all …]
H A Dti,phy-j721e-wiz.yaml8 title: TI J721E WIZ (SERDES Wrapper)
61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
118 the SERDES.
148 provided by the SERDES.
166 "^serdes@[0-9a-f]+$":
169 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
173 Torrent SERDES shoul
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H A Drenesas,r8a779f0-ether-serdes.yaml4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
7 title: Renesas Ethernet SERDES
14 const: renesas,r8a779f0-ether-serdes
29 description: Port number of SERDES.
48 compatible = "renesas,r8a779f0-ether-serdes";
/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi367 phys = <&serdes 13>;
374 phys = <&serdes 13>;
381 phys = <&serdes 13>;
388 phys = <&serdes 13>;
395 phys = <&serdes 14>;
402 phys = <&serdes 14>;
409 phys = <&serdes 14>;
416 phys = <&serdes 14>;
423 phys = <&serdes 15>;
430 phys = <&serdes 15>;
[all …]
H A Dsparx5_pcb134_board.dtsi726 phys = <&serdes 13>;
736 phys = <&serdes 14>;
745 phys = <&serdes 15>;
754 phys = <&serdes 16>;
763 phys = <&serdes 17>;
772 phys = <&serdes 18>;
781 phys = <&serdes 19>;
790 phys = <&serdes 20>;
799 phys = <&serdes 21>;
808 phys = <&serdes 22>;
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h428 /* [0x5c] SerDes TX FIFO control */
430 /* [0x60] SerDes TX FIFO status */
432 /* [0x64] SerDes in/out selection */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
625 * [0x88] SERDES 32-bit interface bit selection
646 /* [0xb0] External SERDES control */
788 * Determines the offset of the TBI bus on the SerDes interface:
808 * Determines the offset of the TBI bus on the SerDes interface:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-xgbe-b.dtsi40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Damd-xgbe.txt8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
43 - amd,serdes-blwc: Baseline wandering correction enablement
46 - amd,serdes-cdr-rate: CDR rate speed selection
47 - amd,serdes-pq-skew: PQ (data sampling) skew
48 - amd,serdes-tx-amp: TX amplitude boost
49 - amd,serdes-dfe-tap-config: DFE taps available to run
50 - amd,serdes-dfe-tap-enable: DFE taps to enable
70 amd,serdes-blwc = <1>, <1>, <0>;
[all …]
H A Dhisilicon-hns-dsaf.txt17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
H A Dmicrochip,sparx5-switch.yaml97 phandle of a Ethernet SerDes PHY. This defines which SerDes
157 phys = <&serdes 13>;
166 phys = <&serdes 29>;
175 phys = <&serdes 30>;
184 phys = <&serdes 31>;
193 phys = <&serdes 32>;
203 phys = <&serdes 0>;
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pci_hostbvar.h97 * Fix L0s to L0 exit transition on SerDes <= rev9 devices.
99 * On these devices, PCIe/SerDes symbol lock can be lost if the
103 * The SerDes RX CDR phase lock timers and proportional/integral
153 * Fix SerDes polarity on SerDes <= rev9 devices.
155 * The SerDes polarity must be saved at device attachment, and
161 * SerDes PLL down flag must be manually disabled (by ChipCommon) on
175 * The PCIe SerDes PLL must be configured to not retry the startup
176 * sequence upon frequency detection failure on SerDes <= rev9 devices
183 * Common flag for quirks that require PCIe SerDes TX
191 * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dlan966x-pcb8290.dts11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
120 phys = <&serdes 0 SERDES6G(1)>;
128 phys = <&serdes 1 SERDES6G(1)>;
136 phys = <&serdes 2 SERDES6G(1)>;
144 phys = <&serdes 3 SERDES6G(1)>;
152 phys = <&serdes 4 SERDES6G(2)>;
160 phys = <&serdes 5 SERDES6G(2)>;
168 phys = <&serdes 6 SERDES6G(2)>;
176 phys = <&serdes 7 SERDES6G(2)>;
180 &serdes {
[all...]
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
155 phys = <&serdes 0 CU(0)>;
162 phys = <&serdes 1 CU(1)>;
169 phys = <&serdes 4 SERDES6G(2)>;
176 phys = <&serdes 5 SERDES6G(2)>;
183 phys = <&serdes 6 SERDES6G(2)>;
190 phys = <&serdes 7 SERDES6G(2)>;
196 &serdes {
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h266 /* Begin: Shared SerDes PHY register definitions */
269 /* SerDes autoneg is different from copper */
287 /* End: Shared SerDes PHY register definitions */
334 /* Begin: PHY register values for the 5708S SerDes PHY */
347 /* 5708S SerDes "Digital" Registers (page 0) */
364 /* 5708S SerDes "Digital 3" Registers (page 2) */
368 /* 5708S SerDes "TX Misc" Registers (page 5) */
374 /* End: PHY register values for the 5708S SerDes PHY */
378 /* Begin: PHY register values for the 5709S SerDes PHY */
381 /* 5709S SerDes "General Purpose Status" Registers */
[all …]
/freebsd/sys/arm/annapurna/alpine/
H A Dalpine_serdes.h32 /* SerDes ETH mode */
39 * Get SerDes group regs base, to be used in relevant Alpine drivers.
46 * Set SerDes ETH mode for an entire group, unless already set
53 /* Lock the all serdes group for using common registers */
56 /* Unlock the all serdes group for using common registers */
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dti,am654-serdes-ctrl.yaml4 $id: http://devicetree.org/schemas/soc/ti/ti,am654-serdes-ctrl.yaml#
7 title: Texas Instruments AM654 Serdes Control Syscon
15 - const: ti,am654-serdes-ctrl
35 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";

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