| /freebsd/sys/dev/aic7xxx/ |
| H A D | aic7xxx_inline.h | 48 /************************* Sequencer Execution Control ************************/
55 * Work around any chip bugs related to halting sequencer execution.
70 * Determine whether the sequencer has halted code execution.
71 * Returns non-zero status if the sequencer is stopped.
80 * Request that the sequencer stop and wait, indefinitely, for it
81 * to stop. The sequencer will only acknowledge that it is paused
83 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
92 * Since the sequencer can disable pausing in a critical section, we in ahc_pause()
102 * Allow the sequencer to continue program execution.
104 * sources that would cause the sequencer t
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| H A D | aic79xx_inline.h | 57 /************************ Sequencer Execution Control *************************/
173 * Determine whether the sequencer has halted code execution.
174 * Returns non-zero status if the sequencer is stopped.
183 * Request that the sequencer stop and wait, indefinitely, for it
184 * to stop. The sequencer will only acknowledge that it is paused
186 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
195 * Since the sequencer can disable pausing in a critical section, we in ahd_pause()
203 * Allow the sequencer to continue program execution.
205 * sources that would cause the sequencer to halt have been
208 * we don't want to release the sequencer before going back
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| H A D | aic7xxx.reg | 275 * These are most likely of interest to the sequencer
565 * Sequencer Control (p. 3-33)
582 * Sequencer RAM Data (p. 3-34)
594 * Sequencer Address Registers (p. 3-35)
843 * The sequencer never saw
1254 * BIOS or are specified by the sequencer code.
1280 * the BIOS. The Sequencer relies on a per-SCB field to
1291 * the BIOS. The Sequencer relies in a per-SCB field to control the
1360 * The last bus phase as seen by the sequencer.
1430 * Kernel and sequencer offsets into the queue of
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| H A D | aic79xx.reg | 115 * Sequencer Interrupt Code
155 * The sequencer never saw
284 * Sequencer Interrupt Status
811 * CMC Sequencer Byte Count
820 * Overlay Sequencer Byte Count
829 * Data Channel Sequencer Byte Count
1003 * SG Sequencer Byte Count
3180 * Sequencer Program Overlay Address.
3191 * Sequencer Control 0
3209 * Sequencer Control 1
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| H A D | aic79xx.c | 72 { ILLOPCODE, "Illegal Opcode in sequencer program" },
73 { SQPARERR, "Sequencer Parity Error" },
100 /* Our Sequencer Program */
299 /************************* Sequencer Execution Control ************************/
301 * Restart the sequencer program from address zero
323 * Ensure that the sequencer's idea of TQINPOS in ahd_restart()
324 * matches our own. The sequencer increments TQINPOS in ahd_restart()
327 * the command arrived but the sequencer to not. in ahd_restart()
337 * Clear any pending sequencer interrupt. It is no in ahd_restart()
490 * We leave the sequencer to cleanup in the case of DMA's to in ahd_flush_qoutfifo()
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| H A D | aic79xx.h | 176 * Sequencer Control Blocks (SCBs) store per-transaction information.
195 * We allocate 256 to simplify the logic in the sequencer
291 * not currently a concern in our sequencer since all chips with
465 * The scb is presented to the sequencer with the dataptr and datacnt
481 * sequencer determines that there is a residual in the transfer, or
485 * Sequencer:
503 /*16*/ uint16_t tag; /* Reused by Sequencer. */
520 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
1036 /* Host and sequencer SCB counts */
1202 * Our qfreeze count. The sequencer compare
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| H A D | aic7xxx.h | 149 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
159 * time. To avoid colliding with a DMA write from the sequencer,
176 * We allocate 256 to simplify the logic in the sequencer
435 * The scb is presented to the sequencer with the dataptr and datacnt
451 * sequencer determines that there is a residual in the transfer, it
455 * Sequencer:
492 * in the sequencer.
1067 * Cached copy of the sequencer control register.
1084 * between the sequencer and kernel.
1115 /* Maximum number of sequencer instruction
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| /freebsd/contrib/lib9p/pytest/ |
| H A D | sequencer.py | 6 # 'SequenceError', 'Sequencer']
282 We also require a Sequencer to pack and unpack the members of
285 >>> qid_s = Sequencer('qid')
307 If an EncDecTyped instance has a conditional sequencer, note
309 the Sequencer example below):
314 >>> bfseq = Sequencer('breakfast')
369 (Sequencer instance). For instance, we can en/de-code
466 class Sequencer(object): class
468 A sequencer is an object that packs (marshals) or unpacks
487 >>> s = Sequencer('monty')
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| H A D | protocol.py | 51 Sequencer('stat')
54 is the sequencer. However, most users should rely on the packers and
58 Sequencer('wirestat')
438 import sequencer
440 SequenceError = sequencer.SequenceError
470 Essentially just a Sequencer, except that we remember
1453 print('sequencer is {0!r}'.format(seq), file=sys.stderr)
1493 The parse fills in a Sequencer instance, and returns a list
1536 encdec = sequencer.EncDecSimple(name, _STRING_MAGIC, aux)
1538 encdec = sequencer.EncDecTyped(cls, name, sub, aux)
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | max77620.txt | 31 The Flexible Power Sequencer (FPS) allows each regulator to power up under
48 a flexible power sequencer timer or a software bit. When a FPS source of
50 power sequencer, the power up and power down delays can be specified in
51 the regulators, GPIOs and clocks flexible power sequencer configuration
56 corresponds to its flexible sequencer configuration register.
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| /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ |
| H A D | qcom,pbs.yaml | 7 title: Qualcomm Technologies, Inc. Programmable Boot Sequencer
13 The Qualcomm Technologies, Inc. Programmable Boot Sequencer (PBS)
|
| /freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | adi,adm1266.yaml | 7 title: Analog Devices ADM1266 Cascadable Super Sequencer with Margin
14 Analog Devices ADM1266 Cascadable Super Sequencer with Margin
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| /freebsd/sys/contrib/device-tree/Bindings/mips/brcm/ |
| H A D | soc.txt | 104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
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| /freebsd/sys/contrib/device-tree/Bindings/hwmon/pmbus/ |
| H A D | ti,ucd90320.yaml | 8 title: UCD90320 power sequencer
14 The UCD90320 is a 32-rail PMBus/I2C addressable power-supply sequencer and
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| /freebsd/sys/dev/sound/midi/ |
| H A D | sequencer.c | 31 * The sequencer personality manager.
77 #include <dev/sound/midi/sequencer.h>
81 #define SND_DEV_SEQ 1 /* Sequencer output /dev/sequencer (FM
85 /* Length of a sequencer event. */
96 /* These are the entries to the sequencer driver. */
112 .d_name = "sequencer",
157 "Midi sequencer");
274 DEFINE_CLASS(sequencer, seq_methods, 0);
351 * The old sequencer use in timer_wait()
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| /freebsd/sys/sys/ |
| H A D | soundcard.h | 311 * IOCTL Commands for /dev/sequencer
366 * Sample loading mechanism for internal synthesizers (/dev/sequencer)
464 * Patch management interface (/dev/sequencer, /dev/patmgr#)
479 * the application using /dev/sequencer and the patch manager daemon
484 * ioctl available through /dev/sequencer also. Avoid using it since it's
485 * extremely hardware dependent. In addition access through /dev/sequencer
492 #define PM_K_EVENT 1 /* Event from the /dev/sequencer driver */
539 * /dev/sequencer is opened or closed. A record with key == PM_K_EVENT is
542 #define PM_E_OPENED 1 /* /dev/sequencer opened */
543 #define PM_E_CLOSED 2 /* /dev/sequencer closed */
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| /freebsd/sys/dev/fb/ |
| H A D | vgareg.h | 54 #define TSIDX (IO_VGA + 0x04) /* timing sequencer idx */
55 #define TSREG (IO_VGA + 0x05) /* timing sequencer data */
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| /freebsd/lib/libpmc/pmu-events/arch/x86/skylake/ |
| H A D | frontend.json | 418 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
429 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
439 …ITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
444 …tches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
451 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
461 …"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). A…
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| /freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/ |
| H A D | frontend.json | 418 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
429 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
439 …ITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
444 …tches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
451 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
461 …"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). A…
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/ |
| H A D | frontend.json | 418 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
429 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
439 …ITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
444 …tches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
451 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
461 …"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). A…
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| /freebsd/share/man/man4/ |
| H A D | ahc.4 | 117 Block Move Instruction Support - Doubles the speed of certain sequencer
124 sequencer.
389 sequencer-code assembler,
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | sysex | 147 >>>4 byte 0x03 PATR (Sequencer Pattern Request)
148 >>>4 byte 0x13 PATD (Sequencer Pattern Dump)
149 >>>4 byte 0x23 PATP (Sequencer Pattern Parameter Change)
150 >>>4 byte 0x33 PATQ (Sequencer Pattern Parameter Inquiry)
151 >>>4 byte 0x73 AFM (Sequencer Pattern Reserved)
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/ |
| H A D | frontend.json | 175 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
187 …Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Co…
197 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
212 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwell/ |
| H A D | frontend.json | 175 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
187 …Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Co…
197 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
212 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/ |
| H A D | frontend.json | 175 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
187 …Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Co…
197 …e being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Co…
212 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|