| /linux/drivers/mmc/host/ |
| H A D | sdhci-of-aspeed-test.c | 8 int rate = 52000000; in aspeed_sdhci_phase_ddr52() local
11 aspeed_sdhci_phase_to_tap(NULL, rate, 0)); in aspeed_sdhci_phase_ddr52()
13 aspeed_sdhci_phase_to_tap(NULL, rate, 1)); in aspeed_sdhci_phase_ddr52()
15 aspeed_sdhci_phase_to_tap(NULL, rate, 2)); in aspeed_sdhci_phase_ddr52()
17 aspeed_sdhci_phase_to_tap(NULL, rate, 3)); in aspeed_sdhci_phase_ddr52()
19 aspeed_sdhci_phase_to_tap(NULL, rate, 4)); in aspeed_sdhci_phase_ddr52()
21 aspeed_sdhci_phase_to_tap(NULL, rate, 5)); in aspeed_sdhci_phase_ddr52()
23 aspeed_sdhci_phase_to_tap(NULL, rate, 23)); in aspeed_sdhci_phase_ddr52()
25 aspeed_sdhci_phase_to_tap(NULL, rate, 24)); in aspeed_sdhci_phase_ddr52()
27 aspeed_sdhci_phase_to_tap(NULL, rate, 25)); in aspeed_sdhci_phase_ddr52()
[all …]
|
| /linux/tools/testing/selftests/tc-testing/tc-tests/actions/ |
| H A D | police.json | 20 "cmdUnderTest": "$TC actions add action police rate 1kbit burst 10k index 1",
23 "matchPattern": "action order [0-9]*: police 0x1 rate 1Kbit burst 10Kb",
46 "$TC actions add action police rate 4Mbit burst 120k index 9"
48 "cmdUnderTest": "$TC actions add action police rate 8kbit burst 24k index 9",
75 "cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 1k index 98",
78 "matchPattern": "action order [0-9]*: police 0x62 rate 90Kbit burst 10Kb mtu 1Kb",
102 …"cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 2kb peakrate 100kbit inde…
105 …"matchPattern": "action order [0-9]*: police 0x3 rate 90Kbit burst 10Kb mtu 2Kb peakrate 100Kbit",
129 … "cmdUnderTest": "$TC actions add action police rate 5kbit burst 6kb peakrate 10kbit index 9",
132 "matchPattern": "action order [0-9]*: police 0x9 rate 5Kb burst 10Kb",
[all …]
|
| H A D | sample.json | 20 "cmdUnderTest": "$TC actions add action sample rate 10 group 1 index 2",
23 "matchPattern": "action order [0-9]+: sample rate 1/10 group 1.*index 2 ref",
47 "cmdUnderTest": "$TC actions add action sample rate 700 group 2 continue index 2",
50 "matchPattern": "action order [0-9]+: sample rate 1/700 group 2 continue.*index 2 ref",
74 "cmdUnderTest": "$TC actions add action sample rate 10000 group 11 drop index 22",
77 "matchPattern": "action order [0-9]+: sample rate 1/10000 group 11 drop.*index 22 ref",
101 "cmdUnderTest": "$TC actions add action sample rate 20000 group 72 reclassify index 100",
104 … "matchPattern": "action order [0-9]+: sample rate 1/20000 group 72 reclassify.*index 100 ref",
128 "cmdUnderTest": "$TC actions add action sample rate 20 group 2 pipe index 100",
131 "matchPattern": "action order [0-9]+: sample rate 1/20 group 2 pipe.*index 100 ref",
[all …]
|
| /linux/drivers/clk/at91/ |
| H A D | clk-audio-pll.c | 10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
22 * rate - rate is adjustable.
23 * clk->rate = parent->rate / (qdpmc + 1)
28 * rate - rate is adjustable.
29 * clk->rate = parent->rate / (qdaudio * div))
216 static int clk_audio_pll_frac_compute_frac(unsigned long rate, in clk_audio_pll_frac_compute_frac() argument
[all …]
|
| /linux/drivers/clk/actions/ |
| H A D | owl-composite.c | 60 long rate; in owl_comp_div_determine_rate() local
62 rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw, in owl_comp_div_determine_rate()
63 req->rate, &req->best_parent_rate); in owl_comp_div_determine_rate()
64 if (rate < 0) in owl_comp_div_determine_rate()
65 return rate; in owl_comp_div_determine_rate()
67 req->rate = rate; in owl_comp_div_determine_rate()
76 return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw, in owl_comp_div_recalc_rate()
80 static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate, in owl_comp_div_set_rate() argument
85 return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw, in owl_comp_div_set_rate()
86 rate, parent_rate); in owl_comp_div_set_rate()
[all …]
|
| H A D | owl-factor.c | 44 unsigned long rate, unsigned long parent_rate) in _get_table_val() argument
54 if ((unsigned long)calc_rate <= rate) { in _get_table_val()
67 struct clk_hw *hw, unsigned long rate, in owl_clk_val_best() argument
75 if (!rate) in owl_clk_val_best()
76 rate = 1; in owl_clk_val_best()
80 bestval = _get_table_val(clkt, rate, parent_rate); in owl_clk_val_best()
85 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
92 * It's the most ideal case if the requested rate can be in owl_clk_val_best()
94 * parent rate, so return the divider immediately. in owl_clk_val_best()
103 if (cur_rate <= rate && cur_rate > best) { in owl_clk_val_best()
[all …]
|
| /linux/drivers/net/wireless/intel/iwlwifi/mvm/ |
| H A D | rs.h | 27 u8 prev_rs; /* previous rate used in rs algo */
28 u8 next_rs; /* next rate used in rs algo */
179 #define is_legacy(rate) is_type_legacy((rate)->type) argument
180 #define is_ht_siso(rate) is_type_ht_siso((rate)->type) argument
181 #define is_ht_mimo2(rate) is_type_ht_mimo2((rate)->type) argument
182 #define is_vht_siso(rate) is_type_vht_siso((rate)->type) argument
183 #define is_vht_mimo2(rate) is_type_vht_mimo2((rate)->type) argument
184 #define is_siso(rate) is_type_siso((rate)->type) argument
185 #define is_mimo2(rate) is_type_mimo2((rate)->type) argument
186 #define is_mimo(rate) is_type_mimo((rate)->type) argument
[all …]
|
| /linux/drivers/clk/ti/ |
| H A D | dpll44xx.c | 34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @hw: pointer to the clock to compute the rate for
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
118 unsigned long rate; in omap4_dpll_regm4xen_recalc() local
126 rate = omap2_get_dpll_rate(clk); in omap4_dpll_regm4xen_recalc()
131 rate *= OMAP4430_REGM4XEN_MULT; in omap4_dpll_regm4xen_recalc()
133 return rate; in omap4_dpll_regm4xen_recalc()
[all …]
|
| H A D | dpll3xxx.c | 176 * bypass mode, the DPLL's rate is set equal to its parent clock's
177 * rate. Waits for the DPLL to report readiness before returning.
493 * omap3_dpll_recalc - recalculate DPLL rate
495 * @parent_rate: clock rate of the DPLL parent
497 * Recalculate and propagate the DPLL rate.
513 * The choice of modes depends on the DPLL's programmed rate: if it is
573 /* Non-CORE DPLL rate set code */
576 * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
577 * @hw: pointer to the clock to determine rate for
578 * @req: target rate request
[all …]
|
| /linux/drivers/staging/rtl8723bs/include/ |
| H A D | hal_com.h | 21 /* Rate */
49 #define HDATA_RATE(rate)\ argument
50 (rate == DESC_RATE1M) ? "CCK_1M" : \
51 (rate == DESC_RATE2M) ? "CCK_2M" : \
52 (rate == DESC_RATE5_5M) ? "CCK5_5M" : \
53 (rate == DESC_RATE11M) ? "CCK_11M" : \
54 (rate == DESC_RATE6M) ? "OFDM_6M" : \
55 (rate == DESC_RATE9M) ? "OFDM_9M" : \
56 (rate == DESC_RATE12M) ? "OFDM_12M" : \
57 (rate == DESC_RATE18M) ? "OFDM_18M" : \
[all …]
|
| /linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | phy.c | 1231 u32 addr, u32 mask, u32 val, u8 *rate, in rtw_phy_get_rate_values_of_txpwr_by_rate() argument
1239 rate[0] = DESC_RATE6M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1240 rate[1] = DESC_RATE9M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1241 rate[2] = DESC_RATE12M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1242 rate[3] = DESC_RATE18M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1249 rate[0] = DESC_RATE24M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1250 rate[1] = DESC_RATE36M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1251 rate[2] = DESC_RATE48M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1252 rate[3] = DESC_RATE54M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1258 rate[0] = DESC_RATE1M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
[all …]
|
| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 66 unsigned long rate, parent_rate; member
101 * so get the parent rate explicitly. in emc_recalc_rate()
112 * Rounds up unless no higher rate exists, in which case down. This way is
113 * safer since things have EMC rate floors. Also don't touch parent_rate
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
143 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
[all …]
|
| /linux/drivers/clk/ |
| H A D | clk-vt8500.c | 131 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, in vt8500_dclk_round_rate() argument
137 if (rate == 0) in vt8500_dclk_round_rate()
140 divisor = *prate / rate; in vt8500_dclk_round_rate()
142 /* If prate / rate would be decimal, incr the divisor */ in vt8500_dclk_round_rate()
143 if (rate * divisor < *prate) in vt8500_dclk_round_rate()
157 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, in vt8500_dclk_set_rate() argument
164 if (rate == 0) in vt8500_dclk_set_rate()
167 divisor = parent_rate / rate; in vt8500_dclk_set_rate()
350 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, in vt8500_find_pll_bits() argument
356 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
[all …]
|
| H A D | clk-fractional-divider_test.c | 14 * requested rate.
19 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; in clk_fd_test_approximation_max_denominator() local
28 rate = 240000000; in clk_fd_test_approximation_max_denominator()
29 parent_rate = (max_n + 1) * rate; /* so that it exceeds the maximum divisor */ in clk_fd_test_approximation_max_denominator()
32 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n); in clk_fd_test_approximation_max_denominator()
43 * requested rate.
48 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; in clk_fd_test_approximation_max_numerator() local
57 rate = 240000000; in clk_fd_test_approximation_max_numerator()
58 parent_rate = rate / (max_m + 1); /* so that it exceeds the maximum numerator */ in clk_fd_test_approximation_max_numerator()
61 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n); in clk_fd_test_approximation_max_numerator()
[all …]
|
| H A D | clk-sparx5.c | 61 unsigned long rate = parent_rate / conf->div; in s5_calc_freq() local
68 rate = mult_frac(rate, divt, divb); in s5_calc_freq()
69 rate = roundup(rate, 1000); in s5_calc_freq()
72 return rate; in s5_calc_freq()
75 static void s5_search_fractional(unsigned long rate, in s5_search_fractional() argument
81 ulong cur_offset, best_offset = rate; in s5_search_fractional()
86 conf->rot_ena = 1; /* Fractional rate */ in s5_search_fractional()
95 cur_offset = abs(rate - conf->freq); in s5_search_fractional()
108 static unsigned long s5_calc_params(unsigned long rate, in s5_calc_params() argument
112 if (parent_rate % rate) { in s5_calc_params()
[all …]
|
| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
50 unsigned long rate, u16 flags) in zynqmp_divider_get_val() argument
56 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in zynqmp_divider_get_val()
57 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); in zynqmp_divider_get_val()
65 return (rate - up_rate) <= (down_rate - rate) ? up : down; in zynqmp_divider_get_val()
68 return DIV_ROUND_CLOSEST(parent_rate, rate); in zynqmp_divider_get_val()
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
75 * @parent_rate: rate of parent clock
114 * zynqmp_clk_divider_round_rate() - Round rate of divider clock
116 * @rate: rate of clock to be set
[all …]
|
| H A D | pll.c | 96 * @rate: Desired clock frequency
99 * Return: Frequency closest to @rate the hardware can generate
101 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, in zynqmp_pll_round_rate() argument
107 /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */ in zynqmp_pll_round_rate()
108 if (rate > PS_PLL_VCO_MAX) { in zynqmp_pll_round_rate()
109 div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX); in zynqmp_pll_round_rate()
110 rate = rate / div; in zynqmp_pll_round_rate()
112 if (rate < PS_PLL_VCO_MIN) { in zynqmp_pll_round_rate()
113 mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); in zynqmp_pll_round_rate()
114 rate = rate * mult; in zynqmp_pll_round_rate()
[all …]
|
| /linux/drivers/net/wireless/realtek/rtlwifi/ |
| H A D | rc.c | 9 *Finds the highest rate index we can use
11 *it to lowest rate CCK_1M, otherwise we set rate to
12 *highest rate based on wireless mode used for iwconfig
13 *show Tx rate.
24 struct ieee80211_tx_rate rate; in _rtl_rc_get_highest_rix() local
42 *this rate is no use for true rate, firmware in _rtl_rc_get_highest_rix()
43 *will control rate at all it just used for in _rtl_rc_get_highest_rix()
45 *2.in rtl_get_tcb_desc when we check rate is in _rtl_rc_get_highest_rix()
46 * 1M we will not use FW rate but user rate. in _rtl_rc_get_highest_rix()
70 ieee80211_rate_set_vht(&rate, in _rtl_rc_get_highest_rix()
[all …]
|
| /linux/sound/soc/mediatek/mt8186/ |
| H A D | mt8186-afe-control.c | 75 unsigned int mt8186_general_rate_transform(struct device *dev, unsigned int rate) in mt8186_general_rate_transform() argument
77 switch (rate) { in mt8186_general_rate_transform()
111 dev_err(dev, "%s(), rate %u invalid, use %d!!!\n", in mt8186_general_rate_transform()
112 __func__, rate, MTK_AFE_RATE_48K); in mt8186_general_rate_transform()
118 static unsigned int tdm_rate_transform(struct device *dev, unsigned int rate) in tdm_rate_transform() argument
120 switch (rate) { in tdm_rate_transform()
158 dev_err(dev, "%s(), rate %u invalid, use %d!!!\n", in tdm_rate_transform()
159 __func__, rate, MTK_AFE_TDM_RATE_48K); in tdm_rate_transform()
165 static unsigned int pcm_rate_transform(struct device *dev, unsigned int rate) in pcm_rate_transform() argument
167 switch (rate) { in pcm_rate_transform()
[all …]
|
| /linux/arch/arm/mach-omap2/ |
| H A D | clkt2xxx_virt_prcm_set.c | 16 * code. However, some notion of "rate set" is probably still necessary
17 * for OMAP2xxx at least. Rate sets should be generalized so they can be
19 * has in the past expressed a preference to use rate sets for OPP changes,
48 * sys_ck_rate: the rate of the external high-frequency clock
58 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
67 * Look for a rate equal or less than the target rate given a configuration set.
73 static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_round_to_table_rate() argument
90 if (ptr->mpu_speed <= rate) in omap2_round_to_table_rate()
96 /* Sets basic clocks based on the specified rate */
97 static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_select_table_rate() argument
[all …]
|
| /linux/arch/arm/mach-omap1/ |
| H A D | clock.h | 40 #define CK_1710 (1 << 4) /* 1710 extra for rate selection */
66 * @rate: current clock rate
68 * @recalc: fn ptr that returns the clock's current rate
69 * @set_rate: fn ptr that can change the clock's current rate
70 * @round_rate: fn ptr that can round the clock's current rate
73 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
75 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
80 unsigned long rate; member
82 unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate);
83 int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
[all …]
|
| H A D | clock.c | 138 static int calc_dsor_exp(unsigned long rate, unsigned long realrate) in calc_dsor_exp() argument
157 if (realrate <= rate) in calc_dsor_exp()
171 /* update locally maintained rate, required by arm_ck for omap1_show_rates() */ in omap1_ckctl_recalc()
172 clk->rate = p_rate / dsor; in omap1_ckctl_recalc()
173 return clk->rate; in omap1_ckctl_recalc()
230 int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_select_table_rate() argument
232 /* Find the highest supported frequency <= rate and switch to it */ in omap1_select_table_rate()
236 ref_rate = ck_ref_p->rate; in omap1_select_table_rate()
238 for (ptr = omap1_rate_table; ptr->rate; ptr++) { in omap1_select_table_rate()
246 if (ptr->rate <= rate) in omap1_select_table_rate()
[all …]
|
| /linux/net/wireless/ |
| H A D | util.c | 1313 static u32 cfg80211_calculate_bitrate_ht(struct rate_info *rate) in cfg80211_calculate_bitrate_ht() argument
1318 if (WARN_ON_ONCE(rate->mcs >= 32)) in cfg80211_calculate_bitrate_ht()
1321 modulation = rate->mcs & 7; in cfg80211_calculate_bitrate_ht()
1322 streams = (rate->mcs >> 3) + 1; in cfg80211_calculate_bitrate_ht()
1324 bitrate = (rate->bw == RATE_INFO_BW_40) ? 13500000 : 6500000; in cfg80211_calculate_bitrate_ht()
1335 if (rate->flags & RATE_INFO_FLAGS_SHORT_GI) in cfg80211_calculate_bitrate_ht()
1342 static u32 cfg80211_calculate_bitrate_dmg(struct rate_info *rate) in cfg80211_calculate_bitrate_dmg() argument
1383 if (WARN_ON_ONCE(rate->mcs >= ARRAY_SIZE(__mcs2bitrate))) in cfg80211_calculate_bitrate_dmg()
1386 return __mcs2bitrate[rate->mcs]; in cfg80211_calculate_bitrate_dmg()
1389 static u32 cfg80211_calculate_bitrate_extended_sc_dmg(struct rate_info *rate) in cfg80211_calculate_bitrate_extended_sc_dmg() argument
[all …]
|
| /linux/drivers/memory/tegra/ |
| H A D | tegra20-emc.c | 181 unsigned long rate; member
217 * a min/max clock rate, these rates are contained in this array.
221 /* protect shared rate-change code path */
257 unsigned long rate) in tegra_emc_find_timing() argument
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
270 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
277 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
279 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in emc_prepare_timing_change()
285 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
286 __func__, timing->rate, rate); in emc_prepare_timing_change()
[all …]
|
| /linux/sound/soc/mediatek/mt8192/ |
| H A D | mt8192-afe-control.c | 45 unsigned int rate) in mt8192_general_rate_transform() argument
47 switch (rate) { in mt8192_general_rate_transform()
81 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", in mt8192_general_rate_transform()
83 rate, MTK_AFE_RATE_48K); in mt8192_general_rate_transform()
89 unsigned int rate) in dai_memif_rate_transform() argument
91 switch (rate) { in dai_memif_rate_transform()
101 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", in dai_memif_rate_transform()
103 rate, MTK_AFE_DAI_MEMIF_RATE_16K); in dai_memif_rate_transform()
109 unsigned int rate) in pcm_rate_transform() argument
111 switch (rate) { in pcm_rate_transform()
[all …]
|