181 	unsigned long rate;  member
217 	 * a min/max clock rate, these rates are contained in this array.
221 	/* protect shared rate-change code path */
257 						unsigned long rate)  in tegra_emc_find_timing()  argument
263 		if (emc->timings[i].rate >= rate) {  in tegra_emc_find_timing()
270 		dev_err(emc->dev, "no timing for rate %lu\n", rate);  in tegra_emc_find_timing()
277 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)  in emc_prepare_timing_change()  argument
279 	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);  in emc_prepare_timing_change()
285 	dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",  in emc_prepare_timing_change()
286 		__func__, timing->rate, rate);  in emc_prepare_timing_change()
359 	u32 rate;  in load_one_timing_from_dt()  local
367 	err = of_property_read_u32(node, "clock-frequency", &rate);  in load_one_timing_from_dt()
369 		dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",  in load_one_timing_from_dt()
385 	 * The EMC clock rate is twice the bus rate, and the bus rate is  in load_one_timing_from_dt()
388 	timing->rate = rate * 2 * 1000;  in load_one_timing_from_dt()
390 	dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",  in load_one_timing_from_dt()
391 		__func__, node, timing->rate);  in load_one_timing_from_dt()
401 	if (a->rate < b->rate)  in cmp_timings()
404 	if (a->rate > b->rate)  in cmp_timings()
448 		      emc->timings[0].rate / 1000000,  in tegra_emc_load_timings_from_dt()
449 		      emc->timings[emc->num_timings - 1].rate / 1000000);  in tegra_emc_load_timings_from_dt()
672 static long emc_round_rate(unsigned long rate,  in emc_round_rate()  argument
684 	min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);  in emc_round_rate()
687 		if (emc->timings[i].rate < rate && i != emc->num_timings - 1)  in emc_round_rate()
690 		if (emc->timings[i].rate > max_rate) {  in emc_round_rate()
693 			if (emc->timings[i].rate < min_rate)  in emc_round_rate()
697 		if (emc->timings[i].rate < min_rate)  in emc_round_rate()
705 		dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",  in emc_round_rate()
706 			rate, min_rate, max_rate);  in emc_round_rate()
710 	return timing->rate;  in emc_round_rate()
751 	 * EMC rate-changes should go via OPP API because it manages voltage  in emc_request_rate()
764 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,  in emc_set_min_rate()  argument
771 	ret = emc_request_rate(emc, rate, req->max_rate, type);  in emc_set_min_rate()
777 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,  in emc_set_max_rate()  argument
784 	ret = emc_request_rate(emc, req->min_rate, rate, type);  in emc_set_max_rate()
815 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)  in tegra_emc_validate_rate()  argument
820 		if (rate == emc->timings[i].rate)  in tegra_emc_validate_rate()
833 		seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);  in tegra_emc_debug_available_rates_show()
843 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)  in tegra_emc_debug_min_rate_get()  argument
847 	*rate = emc->debugfs.min_rate;  in tegra_emc_debug_min_rate_get()
852 static int tegra_emc_debug_min_rate_set(void *data, u64 rate)  in tegra_emc_debug_min_rate_set()  argument
857 	if (!tegra_emc_validate_rate(emc, rate))  in tegra_emc_debug_min_rate_set()
860 	err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);  in tegra_emc_debug_min_rate_set()
864 	emc->debugfs.min_rate = rate;  in tegra_emc_debug_min_rate_set()
873 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)  in tegra_emc_debug_max_rate_get()  argument
877 	*rate = emc->debugfs.max_rate;  in tegra_emc_debug_max_rate_get()
882 static int tegra_emc_debug_max_rate_set(void *data, u64 rate)  in tegra_emc_debug_max_rate_set()  argument
887 	if (!tegra_emc_validate_rate(emc, rate))  in tegra_emc_debug_max_rate_set()
890 	err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);  in tegra_emc_debug_max_rate_set()
894 	emc->debugfs.max_rate = rate;  in tegra_emc_debug_max_rate_set()
913 		if (emc->timings[i].rate < emc->debugfs.min_rate)  in tegra_emc_debugfs_init()
914 			emc->debugfs.min_rate = emc->timings[i].rate;  in tegra_emc_debugfs_init()
916 		if (emc->timings[i].rate > emc->debugfs.max_rate)  in tegra_emc_debugfs_init()
917 			emc->debugfs.max_rate = emc->timings[i].rate;  in tegra_emc_debugfs_init()
928 		dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",  in tegra_emc_debugfs_init()
983 	unsigned long long rate = max(avg_bw, peak_bw);  in emc_icc_set()  local
988 	 * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data  in emc_icc_set()
989 	 * is sampled on both clock edges.  This means that EMC clock rate  in emc_icc_set()
990 	 * equals to the peak data-rate.  in emc_icc_set()
993 	do_div(rate, dram_data_bus_width_bytes);  in emc_icc_set()
994 	rate = min_t(u64, rate, U32_MAX);  in emc_icc_set()
996 	err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);  in emc_icc_set()
1110 	unsigned long rate;  in tegra_emc_devfreq_target()  local
1118 	rate = dev_pm_opp_get_freq(opp);  in tegra_emc_devfreq_target()
1121 	return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);  in tegra_emc_devfreq_target()