176  * bypass mode, the DPLL's rate is set equal to its parent clock's
177  * rate.  Waits for the DPLL to report readiness before returning.
493  * omap3_dpll_recalc - recalculate DPLL rate
495  * @parent_rate: clock rate of the DPLL parent
497  * Recalculate and propagate the DPLL rate.
513  * The choice of modes depends on the DPLL's programmed rate: if it is
573 /* Non-CORE DPLL rate set code */
576  * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
577  * @hw: pointer to the clock to determine rate for
578  * @req: target rate request
580  * Determines which DPLL mode to use for reaching a desired target rate.
582  * locked, calculates the M,N values for the DPLL via round-rate.
591 	if (!req->rate)  in omap3_noncore_dpll_determine_rate()
598 	if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&  in omap3_noncore_dpll_determine_rate()
602 		req->rate = omap2_dpll_round_rate(hw, req->rate,  in omap3_noncore_dpll_determine_rate()
607 	req->best_parent_rate = req->rate;  in omap3_noncore_dpll_determine_rate()
637  * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
639  * @rate: target rate for the clock
640  * @parent_rate: rate of the parent clock
642  * Sets rate for a DPLL clock. First checks if the clock parent is
643  * reference clock (in bypass mode, the rate of the clock can't be
644  * changed) and proceeds with the rate change operation. Returns 0
647 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,  in omap3_noncore_dpll_set_rate()  argument
655 	if (!hw || !rate)  in omap3_noncore_dpll_set_rate()
674 	pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,  in omap3_noncore_dpll_set_rate()
675 		 clk_hw_get_name(hw), rate);  in omap3_noncore_dpll_set_rate()
683  * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
684  * @hw: pointer to the clock to set rate and parent for
685  * @rate: target rate for the DPLL
686  * @parent_rate: clock rate of the DPLL parent
689  * Sets rate and parent for a DPLL clock. If new parent is the bypass
690  * clock, only selects the parent. Otherwise proceeds with a rate
696 					   unsigned long rate,  in omap3_noncore_dpll_set_rate_and_parent()  argument
702 	if (!hw || !rate)  in omap3_noncore_dpll_set_rate_and_parent()
706 	 * clk-ref at index[0], in which case we only need to set rate,  in omap3_noncore_dpll_set_rate_and_parent()
713 		ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);  in omap3_noncore_dpll_set_rate_and_parent()
833  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
835  * @parent_rate: clock rate of the DPLL parent
838  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
844 	unsigned long rate;  in omap3_clkoutx2_recalc()  local
863 		rate = parent_rate;  in omap3_clkoutx2_recalc()
865 		rate = parent_rate * 2;  in omap3_clkoutx2_recalc()
866 	return rate;  in omap3_clkoutx2_recalc()
873  * Before the dpll registers are lost save the last rounded rate m and n
902  * Restore the last rounded rate m and n
934  * Before the dpll registers are lost save the last rounded rate m and n
963  * Restore the last rounded rate m and n
1000  * omap3_dpll4_set_rate - set rate for omap3 per-dpll
1002  * @rate: target rate for clock
1003  * @parent_rate: clock rate of the DPLL parent
1006  * or not, and then do the rate change if supported. Returns -EINVAL
1008  * clock rate change.
1010 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,  in omap3_dpll4_set_rate()  argument
1019 		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");  in omap3_dpll4_set_rate()
1023 	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);  in omap3_dpll4_set_rate()
1027  * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
1029  * @rate: target rate for clock
1030  * @parent_rate: rate of the parent clock
1034  * or not, and then do the rate + parent change if supported. Returns
1036  * from the clock rate change.
1038 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,  in omap3_dpll4_set_rate_and_parent()  argument
1042 		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");  in omap3_dpll4_set_rate_and_parent()
1046 	return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,  in omap3_dpll4_set_rate_and_parent()
1055 		unsigned int rate, m, n;  in omap3_dpll5_apply_errata()  member
1078 		if (parent_rate == precomputed[i].rate)  in omap3_dpll5_apply_errata()
1087 	/* Update the M, N and rounded rate values and program the DPLL. */  in omap3_dpll5_apply_errata()
1098  * omap3_dpll5_set_rate - set rate for omap3 dpll5
1100  * @rate: target rate for clock
1101  * @parent_rate: rate of the parent clock
1103  * Set rate for the DPLL5 clock. Apply the sprz319 advisory 2.1 on OMAP36xx if
1104  * the DPLL is used for USB host (detected through the requested rate).
1106 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,  in omap3_dpll5_set_rate()  argument
1109 	if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {  in omap3_dpll5_set_rate()
1114 	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);  in omap3_dpll5_set_rate()