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/freebsd/lib/libc/arm/aeabi/
H A Daeabi_vfp.h53 #define LOAD_DREG(vreg, reg0, reg1) vmov vreg, reg1, reg0 argument
54 #define UNLOAD_DREG(reg0, reg1, vreg) vmov reg1, reg0, vreg argument
56 #define LOAD_DREG(vreg, reg0, reg1) vmov vreg, reg0, reg1 argument
57 #define UNLOAD_DREG(reg0, reg1, vreg) vmov reg0, reg1, vreg argument
60 #define LOAD_SREGS(vreg0, vreg1, reg0, reg1) vmov vreg0, vreg1, reg0, reg1 argument
/freebsd/crypto/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
490 reg1 = GET_U32_BE(in, 1); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
516 reg1 = rk->u[1] ^ MAKE_U32( in ossl_aria_encrypt()
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/freebsd/sys/arm/ti/am335x/
H A Dam335x_pmic.c141 struct tps65217_chgconfig1_reg reg1; in am335x_pmic_dump_chgconfig() local
167 am335x_pmic_read(dev, TPS65217_CHGCONFIG1_REG, (uint8_t *)&reg1, 1); in am335x_pmic_dump_chgconfig()
168 device_printf(dev, " Charger: %s\n", d_e[reg1.chg_en]); in am335x_pmic_dump_chgconfig()
169 device_printf(dev, " Suspend charge: %s\n", i_a[reg1.susp]); in am335x_pmic_dump_chgconfig()
170 device_printf(dev, " Charge termination: %s\n", e_d[reg1.term]); in am335x_pmic_dump_chgconfig()
171 device_printf(dev, " Charger reset: %s\n", i_a[reg1.reset]); in am335x_pmic_dump_chgconfig()
172 device_printf(dev, " NTC TYPE: %s\n", ntc_type_c[reg1.ntc_type]); in am335x_pmic_dump_chgconfig()
173 device_printf(dev, " Safety timer: %s\n", d_e[reg1.tmr_en]); in am335x_pmic_dump_chgconfig()
174 device_printf(dev, " Charge safety timer: %s\n", timer_c[reg1.timer]); in am335x_pmic_dump_chgconfig()
/freebsd/crypto/openssl/crypto/perlasm/
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp427 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
1017 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is in parseAddress()
1018 // always a general register. Reg1 should be of group RegV if "HasVectorIndex" in parseAddress()
1028 if (parseRegister(Reg1)) in parseAddress()
1047 if (parseIntegerRegister(Reg1, RegGroup)) in parseAddress()
1102 Register Reg1, Reg2; in parseAddress() local
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1122 // If we have Reg1, it must be an address register. in parseAddress()
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/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_hsi_iscsi.h291 __le32 reg1 /* reg1 */; member
410 __le32 reg1 /* reg1 */; member
486 __le32 reg1 /* reg1 */; member
536 __le32 reg1 /* reg1 */; member
804 __le32 reg1 /* reg1 */; member
954 __le32 reg1 /* reg1 */; member
1039 __le32 reg1 /* reg1 */; member
1081 __le32 reg1 /* reg1 */; member
1154 __le32 reg1 /* reg1 */; member
1199 __le32 reg1 /* reg1 */; member
H A Decore_hsi_roce.h529 __le32 reg1 /* reg1 */; member
567 __le32 reg1 /* reg1 */; member
655 __le32 snd_nxt_psn /* reg1 */;
760 __le32 reg1 /* reg1 */; member
843 __le32 reg1 /* reg1 */; member
913 __le32 reg1 /* reg1 */; member
1142 __le32 ssn /* reg1 */;
1374 __le32 rxmit_bytes_length /* reg1 */;
1418 __le32 reg1 /* reg1 */; member
1463 __le32 reg1 /* reg1 */; member
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H A Decore_hsi_rdma.h97 __le32 fbo_lo /* reg1 */;
154 __le32 fbo_lo /* reg1 */;
226 __le32 dif_error_1st_interval /* reg1 */;
317 __le32 fbo_lo /* reg1 */;
388 __le32 fbo_lo /* reg1 */;
1007 __le32 reg1 /* reg1 */; member
1048 __le32 reg1 /* reg1 */; member
1136 __le32 reg1 /* reg1 */; member
1232 __le32 reg1 /* reg1 */; member
1299 __le32 cq_se_prod /* reg1 */;
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H A Decore_hsi_fcoe.h462 __le32 reg1 /* reg1 */; member
574 __le32 reg1 /* reg1 */; member
640 __le32 reg1 /* reg1 */; member
713 __le32 reg1 /* reg1 */; member
1009 __le32 reg1 /* reg1 */; member
1218 __le32 reg1 /* reg1 */; member
1260 __le32 reg1 /* reg1 */; member
1379 __le32 reg1 /* reg1 */; member
1424 __le32 reg1 /* reg1 */; member
H A Decore_hsi_iwarp.h293 __le32 reg1 /* reg1 */; member
412 __le32 reg1 /* reg1 */; member
699 __le32 reg1 /* reg1 */; member
849 __le32 reg1 /* reg1 */; member
1264 __le32 reg1 /* reg1 */; member
1330 __le32 cq_se_prod /* reg1 */;
1373 __le32 reg1 /* reg1 */; member
1417 __le32 reg1 /* reg1 */; member
1495 __le32 cq_se_prod /* reg1 */;
1538 __le32 reg1 /* reg1 */; member
H A Decore_hsi_eth.h284 __le32 reg1 /* reg1 */; member
368 __le32 reg1 /* reg1 */; member
462 __le32 reg1 /* reg1 */; member
545 __le32 reg1 /* reg1 */; member
810 __le32 reg1 /* reg1 */; member
966 __le32 reg1 /* reg1 */; member
1021 __le32 reg1 /* reg1 */; member
1105 __le32 reg1 /* reg1 */; member
1987 __le32 reg1 /* reg1 */; member
2028 __le32 reg1 /* reg1 */; member
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp672 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
697 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
700 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
703 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
706 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
709 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
712 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
716 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
723 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
726 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Drockchip,rk806.yaml36 The input supply for dcdc-reg1.
76 The input supply for pldo-reg1, pldo-reg2 and pldo-reg3.
84 The input supply for nldo-reg1, nldo-reg2 and nldo-reg3.
159 vdd_gpu_s0: dcdc-reg1 {
279 avcc_1v8_s0: pldo-reg1 {
353 vdd_0v75_s3: nldo-reg1 {
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h129 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
131 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
137 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
139 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
281 // li reg1, constant in adjustStackPtrBig()
283 // add reg1, reg1, reg2 in adjustStackPtrBig()
284 // move sp, reg1 in adjustStackPtrBig()
287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
292 MIB3.addReg(Reg1); in adjustStackPtrBig()
296 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1247 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
1250 .addImm(Reg1) in InsertSEH()
1260 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
1261 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1268 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
1298 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1301 .addImm(Reg1) in InsertSEH()
1309 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1310 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1317 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
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H A DAArch64LowerHomogeneousPrologEpilog.cpp205 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
207 assert(Reg1 != AArch64::NoRegister); in emitStore()
209 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitStore()
236 MIB.addReg(Reg1) in emitStore()
246 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
248 assert(Reg1 != AArch64::NoRegister); in emitLoad()
250 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitLoad()
277 MIB.addReg(Reg1, getDefRegState(true)) in emitLoad()
/freebsd/contrib/one-true-awk/testdir/
H A DT.recache26 reg1 = "[Aa]"
28 sub(reg1, x ~ reg2 ? "B" : "b", x)
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dspectral.c71 u32 reg0, reg1; in ath10k_spectral_process_fft() local
83 reg1 = __le32_to_cpu(fftr->reg1); in ath10k_spectral_process_fft()
114 fft_sample->relpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB); in ath10k_spectral_process_fft()
115 fft_sample->avgpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB); in ath10k_spectral_process_fft()
117 peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); in ath10k_spectral_process_fft()
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dactive-semi,act8846.yaml41 description: Handle to the VP1 input supply (REG1)
82 REG1 {
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dsamsung-mipi-csis.txt54 reg1: regulator@1 {
72 vddcore-supply = <&reg1>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
220 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
238 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
248 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
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