427   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,  in parseAddress()  argument
1017   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is  in parseAddress()
1018   // always a general register. Reg1 should be of group RegV if "HasVectorIndex"  in parseAddress()
1028       if (parseRegister(Reg1))  in parseAddress()
1047         if (parseIntegerRegister(Reg1, RegGroup))  in parseAddress()
1102   Register Reg1, Reg2;  in parseAddress()  local
1109   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,  in parseAddress()
1122     // If we have Reg1, it must be an address register.  in parseAddress()
1124       if (parseAddressRegister(Reg1))  in parseAddress()
1126       Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];  in parseAddress()
1133     // If we have Reg1, it must be an address register.  in parseAddress()
1135       if (parseAddressRegister(Reg1))  in parseAddress()
1140         Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];  in parseAddress()
1142         Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];  in parseAddress()
1166     // We must have Reg1, and it must be a GPR.  in parseAddress()
1167     if (!HaveReg1 || Reg1.Group != RegGR)  in parseAddress()
1169     LengthReg = SystemZMC::GR64Regs[Reg1.Num];  in parseAddress()
1178     // We must have Reg1, and it must be a vector register.  in parseAddress()
1179     if (!HaveReg1 || Reg1.Group != RegV)  in parseAddress()
1181     Index = SystemZMC::VR128Regs[Reg1.Num];  in parseAddress()
1495   Register Reg1, Reg2;  in parseOperand()  local
1499   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,  in parseOperand()
1504   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV  in parseOperand()
1505       && parseAddressRegister(Reg1))  in parseOperand()