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/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
80 &rcc {
81 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f769.dtsi15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
H A Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-ed1-scmi.dts38 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
76 &rcc {
77 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
105 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32mp157f-dk2-scmi.dtsi52 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
72 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
98 &rcc {
99 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp135.dtsi15 resets = <&rcc DCMIPP_R>;
16 clocks = <&rcc DCMIPP_K>;
28 clocks = <&rcc LTDC_PX>;
H A Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32mp151c-mecio1r0.dts44 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL3_Q>;
45 assigned-clock-parents = <&rcc PLL3_Q>;
H A Dstm32f769-disco.dts107 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
119 &rcc {
120 compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml105 select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
106 RCC clock instead of ETH_CLK125.
111 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
117 select RCC clock instead of ETH_REF_CLK.
178 clocks = <&rcc ETHMAC>,
179 <&rcc ETHTX>,
180 <&rcc ETHRX>,
181 <&rcc ETHSTP>,
182 <&rcc ETHCK_K>;
199 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dst,stm32-i2c.yaml145 #include <dt-bindings/mfd/stm32f7-rcc.h>
153 resets = <&rcc 277>;
154 clocks = <&rcc 0 149>;
160 #include <dt-bindings/mfd/stm32f7-rcc.h>
168 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
169 clocks = <&rcc 1 CLK_I2C1>;
175 #include <dt-bindings/mfd/stm32f7-rcc.h>
186 clocks = <&rcc I2C2_K>;
187 resets = <&rcc I2C2_R>;
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
H A Dstm32mp233.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32mp21-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#
13 The RCC hardware block is both a reset and a clock controller.
14 RCC makes also power management (resume/suspend).
17 include/dt-bindings/clock/st,stm32mp21-rcc.h
18 include/dt-bindings/reset/st,stm32mp21-rcc.h
23 - st,stm32mp21-rcc
121 #include <dt-bindings/clock/st,stm32mp21-rcc.h>
124 compatible = "st,stm32mp21-rcc";
H A Dst,stm32mp25-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
13 The RCC hardware block is both a reset and a clock controller.
14 RCC makes also power management (resume/suspend).
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
131 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
134 compatible = "st,stm32mp25-rcc";
/linux/Documentation/devicetree/bindings/rtc/
H A Dst,stm32-rtc.yaml148 #include <dt-bindings/mfd/stm32f4-rcc.h>
153 clocks = <&rcc 1 CLK_RTC>;
154 assigned-clocks = <&rcc 1 CLK_RTC>;
155 assigned-clock-parents = <&rcc 1 CLK_LSE>;
167 clocks = <&rcc RTCAPB>, <&rcc RTC>;
/linux/Documentation/devicetree/bindings/pci/
H A Dst,stm32-pcie-ep.yaml52 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
55 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
64 clocks = <&rcc CK_BUS_PCIE>;
66 resets = <&rcc PCIE_R>;
H A Dst,stm32-pcie-host.yaml72 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
76 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
96 clocks = <&rcc CK_BUS_PCIE>;
97 resets = <&rcc PCIE_R>;
/linux/Documentation/devicetree/bindings/media/
H A Dst,stm32-dma2d.yaml61 #include <dt-bindings/mfd/stm32f4-rcc.h>
66 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
67 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;

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