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/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
48 Include support for the ARM(R) Integrator/AP and
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
61 allows ARM(R) Ltd PrimeCells to be developed and evaluated.
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Dmsm_media_info.h5 #define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\
6 ((((__sz) + (__align) - 1) / (__align)) * (__align)) :\
7 (((__sz) + (__align) - 1) & (~((__align) - 1))))
11 #define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r))
24 * <-------- Y/UV_Stride -------->
25 * <------- Width ------->
44 * . . . . . . . . . . . . . . . . --> Buffer size alignment
50 * Extradata: Arbitrary (software-imposed) padding
62 * <-------- Y/UV_Stride -------->
63 * <------- Width ------->
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/linux/drivers/gpu/drm/xe/
H A Dxe_svm.c1 // SPDX-License-Identifier: MIT
31 .__flags = READ_ONCE(range->base.pages.flags.__flags), in xe_svm_range_in_vram()
40 return xe_svm_range_in_vram(range) && range->tile_present; in xe_svm_range_has_vram_binding()
48 static struct xe_vm *range_to_vm(struct drm_gpusvm_range *r) in range_to_vm() argument
50 return gpusvm_to_vm(r->gpusvm); in range_to_vm()
54 vm_dbg(&range_to_vm(&(r__)->base)->xe->drm, \
57 (operation__), range_to_vm(&(r__)->base)->usm.asid, \
58 (r__)->base.gpusvm, \
61 (r__)->base.pages.notifier_seq, \
79 INIT_LIST_HEAD(&range->garbage_collector_link); in xe_svm_range_alloc()
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H A Dxe_svm.h1 /* SPDX-License-Identifier: MIT */
12 * xe_svm_devm_owner() - Return the owner of device private memory
16 * hmm_range_fault()-
37 /** struct xe_svm_range - SVM range */
47 * @tile_present: Tile mask of binding is present for this range.
52 * @tile_invalidated: Tile mask of binding is invalidated for this
59 * xe_svm_range_pages_valid() - SVM range pages valid
66 return drm_gpusvm_range_pages_valid(range->base.gpusvm, &range->base); in xe_svm_range_pages_valid()
69 int xe_devm_add(struct xe_tile *tile, struct xe_vram_region *vr);
87 int xe_svm_alloc_vram(struct xe_tile *tile, struct xe_svm_range *range,
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H A Dxe_guc.c1 // SPDX-License-Identifier: MIT
54 * For most BOs, the address on the allocating tile is fine. However for in guc_bo_ggtt_addr()
55 * some, e.g. G2G CTB, the address on a specific tile is required as it in guc_bo_ggtt_addr()
56 * might be different for each tile. So, just always ask for the address in guc_bo_ggtt_addr()
59 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); in guc_bo_ggtt_addr()
64 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); in guc_bo_ggtt_addr()
71 u32 level = xe_guc_log_get_level(&guc->log); in guc_ctl_debug_flags()
87 if (!xe->info.skip_guc_pc) in guc_ctl_feature_flags()
90 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) in guc_ctl_feature_flags()
98 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; in guc_ctl_log_params_flags()
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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
132 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1…
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c892 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
895 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
896 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
897 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
904 * gfx_v7_0_init_microcode - load ucode images from disk
919 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
939 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v7_0_init_microcode()
945 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v7_0_init_microcode()
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H A Damdgpu_display.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
52 * amdgpu_display_hotplug_work_func - work handler for display hotplug event
72 struct drm_mode_config *mode_config = &dev->mode_config; in amdgpu_display_hotplug_work_func()
76 mutex_lock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
81 mutex_unlock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
98 schedule_work(&work->flip_work.work); in amdgpu_display_flip_callback()
111 if (!dma_fence_add_callback(fence, &work->cb, in amdgpu_display_flip_handle_fence()
125 struct amdgpu_device *adev = work->adev; in amdgpu_display_flip_work_func()
126 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; in amdgpu_display_flip_work_func()
128 struct drm_crtc *crtc = &amdgpu_crtc->base; in amdgpu_display_flip_work_func()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence.h>
7 #include <linux/dma-resv.h>
26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
31 * the cache-line pairs. The compression state of the cache-line pair
32 * is specified by 2 bits in the CCS. Each CCS cache-line represents
33 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
34 * cache-line-pairs. CCS is always Y tiled."
62 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
63 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
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/linux/Documentation/userspace-api/
H A Ddma-buf-alloc-exchange.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. Copyright 2021-2023 Collabora Ltd.
9 support for sharing pixel-buffer allocations between processes, devices, and
12 approach this sharing for two-dimensional image data.
25 Conceptually a two-dimensional array of pixels. The pixels may be stored
30 A span along a single y-axis value, e.g. from co-ordinates (0,100) to
37 A span along a single x-axis value, e.g. from co-ordinates (100,0) to
46 A two-dimensional array of some or all of an image's color and alpha
51 more color channels values, e.g. R, G and B, or Y, Cb and Cr. May also
65 channels R, G, and B. Alpha channel is sometimes counted as a color
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/linux/arch/riscv/kernel/
H A Dptrace.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copied from arch/tile/kernel/ptrace.c
52 return user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs, 0, -1); in riscv_gpr_set()
60 struct __riscv_d_ext_state *fstate = &target->thread.fstate; in riscv_fpr_get()
66 membuf_store(&to, fstate->fcsr); in riscv_fpr_get()
76 struct __riscv_d_ext_state *fstate = &target->thread.fstate; in riscv_fpr_set()
83 sizeof(fstate->fcsr)); in riscv_fpr_set()
95 struct __riscv_v_ext_state *vstate = &target->thread.vstate; in riscv_vr_get()
99 return -EINVAL; in riscv_vr_get()
107 riscv_v_vstate_save(&current->thread.vstate, task_pt_regs(current)); in riscv_vr_get()
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_frontend.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
59 * The first three values of each row are coded as 13-bit signed fixed-point
61 * constant coded as a 14-bit signed fixed-point number with 4 bits for the
65 * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
66 * R = 1.164 * Y + 1.596 * V - 222
83 if (frontend->data->has_coef_access_ctrl) in sun4i_frontend_scaler_init()
84 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG, in sun4i_frontend_scaler_init()
89 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i), in sun4i_frontend_scaler_init()
91 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i), in sun4i_frontend_scaler_init()
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/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
11 #include <media/videobuf2-core.h>
12 #include "mtk-img-ipi.h"
17 * H-subsample: 0, 1, 2
18 * V-subsample: 0, 1
19 * Color group: 0-RGB, 1-YUV, 2-raw
107 /* For bayer+mono raw-16 */
159 /* Packed 10-bit formats */
162 /* Packed 10-bit UYVY */
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/linux/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
46 (((pcie)->hip_base) + (reg) + (1 << 20))
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg))
151 writel_relaxed(value, pcie->cra_base + reg); in cra_writel()
156 return readl_relaxed(pcie->cra_base + reg); in cra_readl()
162 writew_relaxed(value, pcie->cra_base + reg); in cra_writew()
167 return readw_relaxed(pcie->cra_base + reg); in cra_readw()
173 writeb_relaxed(value, pcie->cra_base + reg); in cra_writeb()
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_kms.c51 * radeon_driver_unload_kms - Main unload function for KMS.
63 struct radeon_device *rdev = dev->dev_private; in radeon_driver_unload_kms()
68 if (rdev->rmmio == NULL) in radeon_driver_unload_kms()
72 pm_runtime_get_sync(dev->dev); in radeon_driver_unload_kms()
73 pm_runtime_forbid(dev->dev); in radeon_driver_unload_kms()
81 if (rdev->agp) in radeon_driver_unload_kms()
82 arch_phys_wc_del(rdev->agp->agp_mtrr); in radeon_driver_unload_kms()
83 kfree(rdev->agp); in radeon_driver_unload_kms()
84 rdev->agp = NULL; in radeon_driver_unload_kms()
87 dev->dev_private = NULL; in radeon_driver_unload_kms()
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H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
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H A Dr300_reg.h95 /* State based - direct writes to registers trigger vertex
107 /* index size - when not set the indices are assumed to be 16 bit */
147 /* BEGIN: Vertex data assembly - lots of uncertainties */
207 * - always set up to produce at least two attributes:
209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
307 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
330 # define R300_2288_R300 0x00750000 /* -- nh */
331 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
381 /* These are values from r300_reg/r300_reg.h - they are known to be correct
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/linux/arch/x86/kvm/
H A Dcpuid.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
55 cpuid_count(0xD, i, &xs->eax, &xs->ebx, &xs->ecx, &ign); in kvm_init_xstate_sizes()
74 offset = (xs->ecx & 0x2) ? ALIGN(ret, 64) : ret; in xstate_required_size()
76 offset = xs->ebx; in xstate_required_size()
77 ret = max(ret, offset + xs->eax); in xstate_required_size()
91 * KVM has a semi-arbitrary rule that querying the guest's CPUID model in kvm_find_cpuid_entry2()
95 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break in kvm_find_cpuid_entry2()
105 if (e->function != function) in kvm_find_cpuid_entry2()
113 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) in kvm_find_cpuid_entry2()
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/linux/include/uapi/linux/
H A Dkfd_ioctl.h30 * - 1.1 - initial version
31 * - 1.3 - Add SMI events support
32 * - 1.4 - Indicate new SRAM EDC bit in device properties
33 * - 1.5 - Add SVM API
34 * - 1.6 - Query clear flags in SVM get_attr API
35 * - 1.7 - Checkpoint Restore (CRIU) API
36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs
37 * - 1.9 - Add available memory ioctl
38 * - 1.10 - Add SMI profiler event log
39 * - 1.11 - Add unified memory for ctx save/restore area
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/linux/mm/
H A Dmm_init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mm_init.c - Memory initialisation verification and debugging
18 #include <linux/page-isolation.h>
79 zonelist = &pgdat->node_zonelists[listid]; in mminit_verify_zonelist()
80 zone = &pgdat->node_zones[zoneid]; in mminit_verify_zonelist()
87 zone->name); in mminit_verify_zonelist()
91 pr_cont("%d:%s ", zone_to_nid(zone), zone->nam in mminit_verify_zonelist()
366 struct memblock_region *r; find_zone_movable_pfns_for_nodes() local
807 static struct memblock_region *r; overlap_memmap_init() local
1244 struct memblock_region *r; zone_absent_pages_in_node() local
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/linux/tools/power/x86/intel-speed-select/
H A Disst-config.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features
55 static int current_clos = -1;
56 static int clos_epp = -1;
57 static int clos_prop_prio = -1;
58 static int clos_min = -1;
59 static int clos_max = -1;
60 static int clos_desired = -1;
168 /* only three CascadeLake-N models are supported */ in update_cpu_model()
175 fp = fopen("/proc/cpuinfo", "r"); in update_cpu_model()
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/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dgnr-metrics.json4 "MetricExpr": "cstate_core@c1\\-residency@ / msr@tsc@",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@",
18 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@",
316 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
329 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
357 …where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operat…
370 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
384 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
389 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
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/linux/tools/perf/scripts/python/
H A Dexported-sql-viewer.py2 # SPDX-License-Identifier: GPL-2.0
3 # exported-sql-viewer.py: view data from sql database
4 # Copyright (c) 2014-2018, Intel Corporation.
7 # export-to-sqlite.py or the export-to-postgresql.py script. Refer to those
11 # call-graph can be displayed for the pt_example database like this:
13 # python tools/perf/scripts/python/exported-sql-viewer.py pt_example
18 # python tools/perf/scripts/python/exported-sql-viewer.py "hostname=myhost username=myuser password…
20 # The result is a GUI window with a tree representing a context-sensitive
21 # call-graph. Expanding a couple of levels of the tree and adjusting column
26 # v- ls
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/linux/drivers/video/fbdev/
H A Dskeletonfb.c2 * linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
61 * Even less warranty that it actually works :-)
107 * This allows when one display changes it video resolution (info->var)
136 * xxxfb_open - Optional function. Called when the framebuffer is
155 * xxxfb_release - Optional function. Called when the framebuffer
174 * xxxfb_check_var - Optional function. Validates a var passed in.
191 * function must return -EINVAL.
196 * a copy of the currently working var (info->var). Better is to not
204 * contents of info->var must be left untouched at all times after
216 * xxxfb_set_par - Optional function. Alters the hardware state.
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
258 /* Enables Display 0 end-of-line-N contribution to
346 (x) * (SCALER_DISPLIST1 - \
353 (x) * (SCALER_DISPLACT1 - \
420 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
426 * channel. Must be 4-pixel aligned.
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