/linux/drivers/crypto/hisilicon/ |
H A D | qm.c | 370 struct hisi_qm *qm; member 386 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number); 387 void (*qm_db)(struct hisi_qm *qm, u16 qn, 389 int (*debug_init)(struct hisi_qm *qm); 390 void (*hw_error_init)(struct hisi_qm *qm); 391 void (*hw_error_uninit)(struct hisi_qm *qm); 392 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm); 393 int (*set_msi)(struct hisi_qm *qm, bool set); 452 static void qm_irqs_unregister(struct hisi_qm *qm); 453 static int qm_reset_device(struct hisi_qm *qm); [all …]
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H A D | debugfs.c | 49 int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name); 117 /* define the QM's dfx regs region and region length */ 153 static void dump_show(struct hisi_qm *qm, void *info, in dump_show() argument 156 struct device *dev = &qm->pdev->dev; in dump_show() 168 static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) in qm_sqc_dump() argument 170 struct device *dev = &qm->pdev->dev; in qm_sqc_dump() 179 if (ret || qp_id >= qm->qp_num) { in qm_sqc_dump() 180 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_sqc_dump() 184 ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1); in qm_sqc_dump() 188 dump_show(qm, &sqc, sizeof(struct qm_sqc), name); in qm_sqc_dump() [all …]
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H A D | qm_common.h | 75 int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op); 76 void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm); 77 void hisi_qm_set_algqos_init(struct hisi_qm *qm);
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H A D | Makefile | 6 hisi_qm-objs = qm.o sgl.o debugfs.o
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/linux/drivers/crypto/hisilicon/sec2/ |
H A D | sec_main.c | 311 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local 313 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show() 399 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument 403 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap() 404 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap() 429 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument 433 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian() 441 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian() 444 static void sec_engine_sva_config(struct hisi_qm *qm) in sec_engine_sva_config() argument 448 if (qm->ver > QM_HW_V2) { in sec_engine_sva_config() [all …]
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H A D | sec.h | 170 struct hisi_qm *qm; member 189 struct hisi_qm qm; member 232 int sec_register_to_crypto(struct hisi_qm *qm); 233 void sec_unregister_from_crypto(struct hisi_qm *qm); 234 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low);
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/linux/drivers/crypto/hisilicon/hpre/ |
H A D | hpre_main.c | 359 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) in hpre_check_alg_support() argument 363 cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; in hpre_check_alg_support() 372 struct hisi_qm *qm = s->private; in hpre_diff_regs_show() local 374 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hpre_diff_regs_show() 459 static void hpre_config_pasid(struct hisi_qm *qm) in hpre_config_pasid() argument 463 if (qm->ver >= QM_HW_V3) in hpre_config_pasid() 466 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid() 467 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid() 468 if (qm->use_sva) { in hpre_config_pasid() 475 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid() [all …]
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H A D | hpre.h | 14 * type used in qm sqc DW6. 71 struct hisi_qm qm; member 104 int hpre_algs_register(struct hisi_qm *qm); 105 void hpre_algs_unregister(struct hisi_qm *qm); 106 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg);
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H A D | hpre_crypto.c | 231 pci_err(qp->qm->pdev, "Can not start qp!\n"); in hpre_get_qp_and_start() 391 ctx->dev = &qp->qm->pdev->dev; in hpre_ctx_set() 393 hpre = container_of(ctx->qp->qm, struct hpre, qm); in hpre_ctx_set() 2105 static int hpre_register_rsa(struct hisi_qm *qm) in hpre_register_rsa() argument 2109 if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP)) in hpre_register_rsa() 2115 dev_err(&qm->pdev->dev, "failed to register rsa (%d)!\n", ret); in hpre_register_rsa() 2120 static void hpre_unregister_rsa(struct hisi_qm *qm) in hpre_unregister_rsa() argument 2122 if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP)) in hpre_unregister_rsa() 2128 static int hpre_register_dh(struct hisi_qm *qm) in hpre_register_dh() argument 2132 if (!hpre_check_alg_support(qm, HPRE_DRV_DH_MASK_CAP)) in hpre_register_dh() [all …]
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/linux/drivers/crypto/hisilicon/zip/ |
H A D | zip_main.c | 348 struct hisi_qm *qm = s->private; in hzip_diff_regs_show() local 350 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hzip_diff_regs_show() 441 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) in hisi_zip_alg_support() argument 445 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val; in hisi_zip_alg_support() 452 static int hisi_zip_set_high_perf(struct hisi_qm *qm) in hisi_zip_set_high_perf() argument 457 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf() 464 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf() 465 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf() 469 pci_err(qm->pdev, "failed to set perf mode\n"); in hisi_zip_set_high_perf() 474 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) in hisi_zip_open_sva_prefetch() argument [all …]
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H A D | zip_crypto.c | 124 dev_dbg(&qp_ctx->qp->qm->pdev->dev, "req cache is full!\n"); in hisi_zip_create_req() 219 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_do_work() 288 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_acomp_cb() 321 struct device *dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_acompress() 342 struct device *dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_adecompress() 363 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_start_qp() 413 hisi_zip = container_of(qps[0]->qm, struct hisi_zip, qm); in hisi_zip_ctx_init() 505 dev = &tmp->qp->qm->pdev->dev; in hisi_zip_create_sgl_pool() 518 hisi_acc_free_sgl_pool(&ctx->qp_ctx[HZIP_QPC_COMP].qp->qm->pdev->dev, in hisi_zip_create_sgl_pool() 528 hisi_acc_free_sgl_pool(&ctx->qp_ctx[i].qp->qm->pdev->dev, in hisi_zip_release_sgl_pool() [all …]
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H A D | zip.h | 27 struct hisi_qm qm; member 85 int hisi_zip_register_to_crypto(struct hisi_qm *qm); 86 void hisi_zip_unregister_from_crypto(struct hisi_qm *qm); 87 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg);
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/linux/include/linux/ |
H A D | hisi_acc_qm.h | 16 /* qm user domain */ 73 /* qm cache */ 251 int (*hw_init)(struct hisi_qm *qm); 252 void (*hw_err_enable)(struct hisi_qm *qm); 253 void (*hw_err_disable)(struct hisi_qm *qm); 254 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm); 255 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts); 256 void (*open_axi_master_ooo)(struct hisi_qm *qm); 257 void (*close_axi_master_ooo)(struct hisi_qm *qm); 258 void (*open_sva_prefetch)(struct hisi_qm *qm); [all …]
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/linux/Documentation/ABI/testing/ |
H A D | debugfs-hisi-sec | 13 has a QM. This file can be used to select the QM which below 14 qm refers to. 27 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_regs 30 Description: Dump of QM related debug registers. 34 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/current_q 37 Description: One QM of SEC may contain multiple queues. Select specific 41 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/clear_enable 45 the SEC's QM debug registers. 49 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/err_irq 53 QM task completion. [all …]
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H A D | debugfs-hisi-zip | 26 has a QM. Select the QM which below qm refers to. 39 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/regs 42 Description: Dump of QM related debug registers. 46 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q 49 Description: One QM may contain multiple queues. Select specific queue to 53 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable 56 Description: QM debug registers(regs) read clear control. 1 means enable 62 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/err_irq 66 QM task completion. 69 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/aeq_irq [all …]
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H A D | debugfs-hisi-hpre | 27 has a QM. Select the QM which below qm refers to. 46 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/regs 49 Description: Dump debug registers from the QM. 53 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/current_q 56 Description: One QM may contain multiple queues. Select specific queue to 60 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/clear_enable 63 Description: QM debug registers(regs) read clear control. 1 means enable 69 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/err_irq 73 QM task completion. 76 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/aeq_irq [all …]
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/linux/drivers/vfio/pci/hisilicon/ |
H A D | hisi_acc_vfio_pci.h | 54 /* QM match information */ 62 /* QM reserved match information */ 65 /* QM RW regs */ 79 /* QM reserved 5 regs */ 82 /* QM memory init information */
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/linux/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_self_test.c | 871 "QM: Queue is not empty", 877 "QM: VOQ_0, VOQ credit is not equal to initial credit", 883 "QM: VOQ_1, VOQ credit is not equal to initial credit", 889 "QM: VOQ_4, VOQ credit is not equal to initial credit", 895 "QM: P0 Byte credit is not equal to initial credit", 901 "QM: P1 Byte credit is not equal to initial credit", 1165 "QM: Interrupt status is not 0", 1201 "QM: Credit error register is not 0 (byte or credit overflow/underflow)", 1861 "QM: XQM wrc_fifolvl is not 0", 1867 "QM: UQM wrc_fifolvl is not 0", [all …]
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H A D | bnx2x_init.h | 178 /* QM queue numbers */ 193 /* QM Register addresses */ 201 /* extracts the QM queue number for the specified port and vnic */ 261 /* Configures the QM according to the specified per-traffic-type COSes */ 308 /* number of bytes in single QM arbitration cycle - 597 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
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H A D | bnx2x_reg.h | 181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 185 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. 235 /* [RW 28] The CM header value for QM request (primary). */ 237 /* [RW 28] The CM header value for QM request (secondary). */ 239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 243 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes 247 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 251 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 266 /* [RW 28] The CM header for QM formatting in case of an error in the QM 1063 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM [all …]
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/linux/drivers/net/ethernet/mediatek/ |
H A D | mtk_wed_debugfs.c | 208 DUMP_STR("WED Route QM"), in wed_rxinfo_show() 245 DUMP_STR("WED Route QM"), in wed_rxinfo_show() 502 DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"), in wed_rtqm_show() 511 DUMP_STR("WED Route QM IGRS1(Legacy)"), in wed_rtqm_show() 520 DUMP_STR("WED Route QM IGRS2(RRO3.0)"), in wed_rtqm_show() 529 DUMP_STR("WED Route QM IGRS3(DEBUG)"), in wed_rtqm_show()
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/linux/Documentation/hwmon/ |
H A D | coretemp.rst | 71 i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105 154 i7 840QM/820/740/720 100
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/linux/fs/xfs/ |
H A D | xfs_stats.c | 57 { "qm", xfsstats_offset(xs_xstrat_bytes)}, in xfs_stats_format() 130 seq_puts(m, "qm"); in xqmstat_proc_show()
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/linux/drivers/media/platform/nxp/imx-jpeg/ |
H A D | Kconfig | 11 This is a video4linux2 driver for the i.MX8 QXP/QM integrated
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/linux/drivers/firmware/imx/ |
H A D | Kconfig | 21 (QM, QP), and i.MX8QX (QXP, DX).
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