| /linux/Documentation/networking/ |
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| H A D | tls-offload-reorder-bad.svg | 1 …q0.28125 1.40625 0.953125 2.015625q0.6875 0.609375 1.65625 0.609375q1.15625 0 1.953125 -0.796875q0…
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| H A D | tls-offload-reorder-good.svg | 1 …q0.28125 1.40625 0.953125 2.015625q0.6875 0.609375 1.65625 0.609375q1.15625 0 1.953125 -0.796875q0…
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| /linux/arch/arm/crypto/ |
| H A D | aes-ce-core.S | 27 enc_round q0, \key1
28 enc_round q0, \key2
32 dec_round q0, \key1
33 dec_round q0, \key2
37 enc_round q0, \key1
38 aese.8 q0, \key2
39 veor q0, q0, \key3
43 dec_round q0, \key1
44 aesd.8 q0, \key2
45 veor q0, q0, \key3
[all …]
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| H A D | aes-neonbs-core.S | 454 vtst.8 q0, q7, q8
463 vmvn q0, q0
469 vst1.8 {q0-q1}, [r0, :256]!
488 veor q10, q0, q9 // xor with round0 key
490 __tbl q0, q10, q8
505 bitslice q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11
517 shift_rows q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12
519 sbox q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, \
524 mix_cols q0, q1, q4, q6, q3, q7, q2, q5, q8, q9, q10, q11, q12, \
534 bitslice q0, q1, q4, q6, q3, q7, q2, q5, q8, q9, q10, q11
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| H A D | blake2b-neon-core.S | 64 // NEON registers q0-q7. The message block is in q8..q15 (M_0-M_15). The stack
77 vadd.u64 q0, q0, q2
85 veor q6, q6, q0
111 vadd.u64 q0, q0, q2
120 veor q6, q6, q0
259 vld1.64 {q0-q1}, [ip]! // Load h[0..3]
275 // entire state matrix in q0-q7 and the entire message block in q8-15.
315 veor q0, q0, q4 // v[0..1] ^= v[8..9]
320 veor q0, q0, q8 // v[0..1] ^= h[0..1]
324 vst1.64 {q0-q1}, [ip]! // Store new h[0..3]
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| /linux/lib/crypto/arm/ |
| H A D | chacha-neon-core.S | 60 * registers q0-q3. It performs matrix operations on four words in parallel,
74 vadd.i32 q0, q0, q1
75 veor q3, q3, q0
85 vadd.i32 q0, q0, q1
86 veor q3, q3, q0
104 vadd.i32 q0, q0, q1
105 veor q3, q3, q0
115 vadd.i32 q0, q0, q1
116 veor q3, q3, q0
148 vld1.32 {q0-q1}, [r0]
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| H A D | curve25519-core.S | 25 vmov.i32 q0, #1
26 vshr.u64 q1, q0, #7
27 vshr.u64 q0, q0, #8
101 vadd.i64 q14, q5, q0
104 vadd.i64 q15, q11, q0
119 vadd.i64 q15, q7, q0
126 vadd.i64 q14, q3, q0
140 vadd.i64 q0, q9, q0
145 vshr.s64 q0, q0, #25
147 vadd.i64 q6, q10, q0
[all …]
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| H A D | sha256-ce.S | 78 0: vld1.32 {q0-q1}, [r1]!
83 vrev32.8 q0, q0
93 vadd.u32 ta0, q0, k0
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| /linux/arch/powerpc/math-emu/ |
| H A D | udivmodti4.c | 14 _FP_W_TYPE q0, q1, r0, r1; in _fp_udivmodti4() local
24 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
37 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
63 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
107 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
122 q0 = 0; in _fp_udivmodti4()
138 quotient digit q0 = 0 or 1). in _fp_udivmodti4()
146 q0 = 1; in _fp_udivmodti4()
150 q0 = 0; in _fp_udivmodti4()
171 udiv_qrnnd (q0, n1, n2, n1, d1); in _fp_udivmodti4()
[all …]
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| /linux/lib/crc/arm/ |
| H A D | crc-t10dif-core.S | 232 vld1.64 {q0-q1}, [buf]!
236 CPU_LE( vrev64.8 q0, q0 )
265 // While >= 128 data bytes remain (not counting q0-q7), fold the 128
266 // bytes q0-q7 into them, storing the result back into q0-q7.
268 fold_32_bytes q0, q1, \p
275 // Now fold the 112 bytes in q0-q6 into the 16 bytes in q7.
279 fold_16_bytes q0, q4, \p
300 vld1.64 {q0}, [buf]!
301 CPU_LE( vrev64.8 q0, q0 )
303 veor.8 q7, q7, q0
[all …]
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| /linux/crypto/ |
| H A D | twofish_common.c | 43 /* These two tables are the q0 and q1 permutations, exactly as described in
46 static const u8 q0[256] = { variable
96 /* These MDS tables are actually tables of MDS composed with q0 and q1,
102 * mds[0][i] = MDS (q1[i] 0 0 0)^T mds[1][i] = MDS (0 q0[i] 0 0)^T
103 * mds[2][i] = MDS (0 0 q1[i] 0)^T mds[3][i] = MDS (0 0 0 q0[i])^T
395 * S-box entries, preprocessed through q0 and q1. */
480 * are the index numbers preprocessed through the q0 and q1 tables
484 ctx->s[0][i] = mds[0][q0[(a) ^ sa] ^ se]; \
485 ctx->s[1][i] = mds[1][q0[(b) ^ sb] ^ sf]; \
492 ctx->s[0][i] = mds[0][q0[q0[(b) ^ sa] ^ se] ^ si]; \
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| H A D | aegis128-neon-inner.c | 13 #define AES_ROUND "aese.8 %q0, %q1 \n\t aesmc.8 %q0, %q0"
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| /linux/drivers/net/ethernet/brocade/bna/ |
| H A D | bna_tx_rx.c | 1617 struct bna_rxq *q0 = NULL, *q1 = NULL; in bna_bfi_rx_enet_start() local
1630 GET_RXQS(rxp, q0, q1); in bna_bfi_rx_enet_start()
1644 &q0->qpt); in bna_bfi_rx_enet_start()
1645 if (q0->multi_buffer) in bna_bfi_rx_enet_start()
1648 * q0->buffer_size should be initialized to in bna_bfi_rx_enet_start()
1654 q0->buffer_size = in bna_bfi_rx_enet_start()
1657 htons((u16)q0->buffer_size); in bna_bfi_rx_enet_start()
1831 bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0, in bna_rxp_add_rxqs() argument
1836 rxp->rxq.single.only = q0; in bna_rxp_add_rxqs()
1840 rxp->rxq.slr.large = q0; in bna_rxp_add_rxqs()
[all …]
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| H A D | bna.h | 181 #define GET_RXQS(rxp, q0, q1) do { \ argument
184 (q0) = rxp->rxq.single.only; \
188 (q0) = rxp->rxq.slr.large; \
192 (q0) = rxp->rxq.hds.data; \
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| /linux/arch/arm/include/asm/ |
| H A D | arch_timer.h | 37 asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val)); in arch_timer_reg_write_cp15()
49 asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val)); in arch_timer_reg_write_cp15()
99 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); in __arch_counter_get_cntpct()
113 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval)); in __arch_counter_get_cntvct()
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| H A D | atomic.h | 320 " " #op1 " %Q0, %Q0, %Q4\n" \
341 " " #op1 " %Q0, %Q0, %Q4\n" \
364 " " #op1 " %Q1, %Q0, %Q5\n" \
464 " subs %Q0, %Q0, #1\n" in arch_atomic64_dec_if_positive()
495 " adds %Q1, %Q0, %Q6\n" in arch_atomic64_fetch_add_unless()
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-srggb8-pisp-comp.rst | 53 Each of the outer samples (q0,q3) is encoded using a 7-bit field based
56 (q0-384). Otherwise for quantization modes 0, 1 and 2: The outer sample
57 is encoded as (q0-MAX(0,q1-64)). q3 is likewise coded based on q2.
68 Each pair of quantized pixels (q0,q1) or (q2,q3) is jointly coded
69 by a 15-bit field: 2816*(q0>>4) + 16*q1 + (q0&15).
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| /linux/arch/arm/mach-pxa/ |
| H A D | pxa27x.c | 129 "mra %Q0, %R0, acc0" : "=r" (acc0)); in pxa27x_cpu_pm_enter()
131 asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0)); in pxa27x_cpu_pm_enter()
153 "mar acc0, %Q0, %R0" : "=r" (acc0)); in pxa27x_cpu_pm_enter()
155 asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0)); in pxa27x_cpu_pm_enter()
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| H A D | pxa3xx.c | 113 "mra %Q0, %R0, acc0" : "=r" (acc0)); in pxa3xx_cpu_pm_suspend()
115 asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0)); in pxa3xx_cpu_pm_suspend()
146 "mar acc0, %Q0, %R0" : "=r" (acc0)); in pxa3xx_cpu_pm_suspend()
148 asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0)); in pxa3xx_cpu_pm_suspend()
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| /linux/arch/x86/include/asm/ |
| H A D | sync_core.h | 28 "pushq %q0\n\t" in iret_to_self()
33 "pushq %q0\n\t" in iret_to_self()
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-latch.yaml | 19 OUT0 ----------------+--|-----------|D0 Q0|-----|<
32 | | | | | | | `--------------|D0 Q0|-----|<
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| /linux/arch/arm/include/asm/vdso/ |
| H A D | cp15.h | 17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
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| /linux/drivers/gpio/ |
| H A D | gpio-latch.c | 13 * OUT0 ----------------+--|-----------|D0 Q0|-----|<
26 * | | | | | | | `--------------|D0 Q0|-----|<
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| /linux/drivers/clk/ |
| H A D | clk-versaclock7.c | 279 u32 q1, q0; in vc7_128_div_64_to_64() local
353 * We wish to compute q0 = [rem1 rem0 n0] / [d1 d0]. in vc7_128_div_64_to_64()
354 * Estimate q0 as [rem1 rem0] / [d1] and correct it. in vc7_128_div_64_to_64()
361 q0 = (u32)qhat; in vc7_128_div_64_to_64()
365 *r = (rem * b + num0 - q0 * den) >> shift; in vc7_128_div_64_to_64()
366 return ((u64)q1 << 32) | q0; in vc7_128_div_64_to_64()
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