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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_dfs.c248 struct mt76x02_dfs_hw_pulse *pulse) in mt76x02_dfs_get_hw_pulse() argument
253 data = (MT_DFS_CH_EN << 16) | pulse->engine; in mt76x02_dfs_get_hw_pulse()
257 pulse->period = mt76_rr(dev, MT_BBP(DFS, 19)); in mt76x02_dfs_get_hw_pulse()
260 pulse->w1 = mt76_rr(dev, MT_BBP(DFS, 20)); in mt76x02_dfs_get_hw_pulse()
261 pulse->w2 = mt76_rr(dev, MT_BBP(DFS, 23)); in mt76x02_dfs_get_hw_pulse()
264 pulse->burst = mt76_rr(dev, MT_BBP(DFS, 22)); in mt76x02_dfs_get_hw_pulse()
268 struct mt76x02_dfs_hw_pulse *pulse) in mt76x02_dfs_check_hw_pulse() argument
272 if (!pulse->period || !pulse->w1) in mt76x02_dfs_check_hw_pulse()
277 if (pulse->engine > 3) in mt76x02_dfs_check_hw_pulse()
280 if (pulse->engine == 3) { in mt76x02_dfs_check_hw_pulse()
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml36 richtek,ld-pulse-delay-us:
38 load current pulse delay in microsecond after strobe pin pulse high.
43 richtek,ld-pulse-width-us:
45 Load current pulse width in microsecond after strobe pin pulse high.
52 Fsin1 pulse high delay in microsecond after vsync signal pulse high.
59 Fsin1 pulse high width in microsecond after vsync signal pulse hig
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_freebsd_inc.h100 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */
104 u_int32_t rp_pulsevar; /* Time variation of pulse duration for
108 u_int32_t rp_mindur; /* Min pulse duration to be considered for
109 this pulse type */
111 this pulse type */
112 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */
123 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */
127 u_int32_t rp_pulsevar; /* Time variation of pulse duration for
131 u_int32_t rp_mindur; /* Min pulse duration to be considered for
132 this pulse type */
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/freebsd/sys/contrib/dev/athk/
H A Ddfs_pattern_detector.h44 * @ts: pulse time stamp in us
46 * @width: pulse duration in us
48 * @chirp: chirp detected in pulse
61 * @width_min: minimum radar pulse width in [us]
62 * @width_max: maximum radar pulse width in [us]
63 * @pri_min: minimum pulse repetition interval in [us] (including tolerance)
68 * @max_pri_tolerance: pulse time stamp tolerance on both sides [us]
88 * @add_pulse(): add radar pulse to detector, returns true on detection
91 * @last_pulse_ts: time stamp of last valid pulse in usecs
H A Ddfs_pri_detector.h27 * @pri: pulse repetition interval (PRI) in usecs
31 * @first_ts: time stamp of first pulse in usecs
32 * @last_ts: time stamp of last pulse in usecs
49 * @add_pulse(): add pulse event, returns pri_sequence if pattern was detected
52 * @last_ts: last pulse time stamp considered for this element in usecs
53 * @sequences: list_head holding potential pulse sequences
57 * @window_size: window size back from newest pulse time stamp in usecs
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-st.txt17 - st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
19 - st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is
39 st,i2c-min-scl-pulse-width-us = <0>;
40 st,i2c-min-sda-pulse-width-us = <5>;
H A Dst,sti-i2c.yaml37 st,i2c-min-scl-pulse-width-us:
39 The minimum valid SCL pulse width that is allowed through the
42 st,i2c-min-sda-pulse-width-us:
44 The minimum valid SDA pulse width that is allowed through the
69 st,i2c-min-scl-pulse-width-us = <0>;
70 st,i2c-min-sda-pulse-width-us = <5>;
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt48 It is the throttling depth of pulse skippers, it's the percentage
51 level of pulse skippers, which used to throttle clock frequencies. It
57 It is the level of pulse skippers, which used to throttle clock
124 * the HW will skip cpu clock's pulse in 85% depth,
125 * skip gpu clock's pulse in 85% level
137 * the HW will skip cpu clock's pulse in 50% depth,
138 * skip gpu clock's pulse in 50% level
151 * settings to skip cpu pulse.
178 * the HW will skip cpu clock's pulse in HIGH level
189 * the HW will skip cpu clock's pulse in MED level
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H A Dnvidia,tegra124-soctherm.yaml91 throttling depth of pulse skippers, it's the percentage
99 of pulse skippers, which used to throttle clock frequencies. It
115 level of pulse skippers, which used to throttle clock
264 * the HW will skip cpu clock's pulse in 85% depth,
265 * skip gpu clock's pulse in 85% level
277 * the HW will skip cpu clock's pulse in 50% depth,
278 * skip gpu clock's pulse in 50% level
291 * settings to skip cpu pulse.
326 * the HW will skip cpu clock's pulse in HIGH level
337 * the HW will skip cpu clock's pulse in MED level
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Datmel,ebi.txt87 - atmel,smc-ncs-rd-pulse-ns
88 - atmel,smc-nrd-pulse-ns
89 - atmel,smc-ncs-wr-pulse-ns
90 - atmel,smc-nwe-pulse-ns
128 atmel,smc-ncs-rd-pulse-ns = <84>;
129 atmel,smc-ncs-wr-pulse-ns = <84>;
130 atmel,smc-nrd-pulse-ns = <76>;
131 atmel,smc-nwe-pulse-ns = <76>;
/freebsd/share/man/man4/
H A Duart.4154 .Sh Pulse Per Second (PPS) Timing Interface
195 Invert the pulse (RS-232 logic low = ASSERT, high = CLEAR).
200 Add the narrow pulse option when the incoming PPS pulse width is small
204 The hardware latch provides a reliable indication that a pulse occurred,
205 but prevents distinguishing between the CLEAR and ASSERT edges of the pulse.
206 For each detected pulse, the driver synthesizes both an ASSERT and a CLEAR
209 see both edges of a pulse, the driver will not generate a new pair of
211 Both normal and narrow pulse modes work with
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstihxxx-b2120.dtsi101 st,i2c-min-scl-pulse-width-us = <0>;
102 st,i2c-min-sda-pulse-width-us = <5>;
108 st,i2c-min-scl-pulse-width-us = <0>;
109 st,i2c-min-sda-pulse-width-us = <5>;
138 st,i2c-min-scl-pulse-width-us = <0>;
139 st,i2c-min-sda-pulse-width-us = <5>;
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Drohm,bd9571mwv.yaml55 rohm,rstbmode-pulse:
58 The RSTB signal is configured for pulse mode, to accommodate a momentary
95 - rohm,rstbmode-pulse
115 rohm,rstbmode-pulse;
H A Dbd9571mwv.txt41 - rohm,rstbmode-pulse: The RSTB signal is configured for pulse mode, to
58 rohm,rstbmode-pulse;
/freebsd/sys/contrib/device-tree/Bindings/ptp/
H A Dptp-qoriq.txt19 - fsl,tmr-fiper1 Fixed interval period pulse generator.
20 - fsl,tmr-fiper2 Fixed interval period pulse generator.
21 - fsl,tmr-fiper3 Fixed interval period pulse generator.
48 Pulse Per Second (PPS) signal, since this will be offered to the PPS
H A Dfsl,ptp.yaml69 description: Fixed interval period pulse generator.
73 description: Fixed interval period pulse generator.
78 Fixed interval period pulse generator.
104 Pulse Per Second (PPS) signal, since this will be offered to the PPS
/freebsd/contrib/ntp/html/
H A Dpps.html6 <title>Pulse-Per-Second (PPS) Signal Interfacing</title>
10 <h3>Pulse-Per-Second (PPS) Signal Interfacing</h3>
24 <li class="inline"><a href="#use">Using the Pulse-per-Second (PPS) Signal</a></li>
28 …e this down to a few tens of microseconds. However, some radios produce a pulse-per-second (PPS) s…
36 …subcircuits. One of these converts a TTL positive edge into a fixed-width pulse at EIA levels and …
41 <h4 id="use">Using the Pulse-per-Second (PPS) Signal</h4>
/freebsd/contrib/ntp/util/
H A Dtg.c72 #define DATA0 200 /* WWV/H 0 pulse */
73 #define DATA1 500 /* WWV/H 1 pulse */
74 #define PI 800 /* WWV/H PI pulse */
75 #define M2 2 /* IRIG 0 pulse */
76 #define M5 5 /* IRIG 1 pulse */
77 #define M8 8 /* IRIG PI pulse */
119 #define MIN 3 /* minute pulse */
129 {MIN, 800}, /* 0 minute sync pulse */
574 * Generate WWV/H 0 or 1 data pulse.
581 * The WWV data pulse begins with 5 ms of 1000 Hz follwed by a in sec()
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/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama5d3xcm.dtsi69 atmel,smc-ncs-rd-pulse-ns = <84>;
70 atmel,smc-ncs-wr-pulse-ns = <84>;
71 atmel,smc-nrd-pulse-ns = <76>;
72 atmel,smc-nwe-pulse-ns = <76>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dawinic,aw8738.yaml14 (set using one-wire pulse control). The mode configures the speaker-guard
26 GPIO used for one-wire pulse control. The pin is typically called SHDN
32 description: Operation mode (number of pulses for one-wire pulse control)
/freebsd/contrib/ntp/html/drivers/
H A Ddriver36.html30 … 1000-Hz pulse, which occurs at the beginning of each second, a 800-ms, 1000-Hz pulse, which occur…
34 …pulse is extracted using an 800-ms synchronous matched filter and pulse grooming logic which discr…
35 <p>The phase of the 100-Hz subcarrier relative to the second pulse is fixed at the transmitter; how…
36 …pulse-width discriminator. The discriminator samples the I channel at 15 ms (<i>n</i>), 200 ms (<…
43 …dependently of the data recovery functions. The maximum value of the 5-ms pulse after the comb fil…
49 …pulse amplitude and SNR measured in second 0 of the minute, together with the data subcarrier ampl…
50 …on represents the high order bits of the metric, while the current minute pulse amplitude represen…
62 …k is set, the time and frequency are disciplined only by the second synch pulse and the clock digi…
76 …t> audio gain, <tt>epoch </tt>second epoch, <tt>secamp/secsnr </tt>second pulse amplitude/SNR, and…
78 …>metric</tt> is described above, and <tt>minamp/minsnr</tt> is the minute pulse ampliture/SNR. An …
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H A Ddriver22.html23 …tricate configuration and was poorly documented. This driver requires the Pulse per Second API (PP…
25 <p>This driver furnishes an interface for the pulse-per-second (PPS) signal produced by a cesium cl…
27 …ietary versions of Tru64 (Alpha) and SunOS. See the <a href="../pps.html">Pulse-per-second (PPS) S…
80 <dd>Specifies PPS capture on the rising (assert) pulse edge if 0 (default) or falling
81 …(clear) pulse edge if 1. Not used under Windows - if the special <tt>serialpps.sys</tt> serial po…
93 …<li>Mogul, J., D. Mills, J. Brittenson, J. Stone and U. Windl. Pulse-per-second API for Unix-like …
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Daspeed-wdt.txt41 - aspeed,ext-pulse-duration: External signal pulse duration in microseconds
47 is configured as push-pull, then set the pulse
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml36 CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
41 CKE minimum pulse width during SELF REFRESH (low pulse width during
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h212 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
214 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */
216 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */
230 #define AR_PHY_RADAR_2_MAXLEN 0x000000FF /* Max Pulse duration threshold */
232 #define AR_PHY_RADAR_2_RELSTEP 0x00001F00 /* Pulse relative step threshold */
234 #define AR_PHY_RADAR_2_RELPWR 0x003F0000 /* pulse relative power threshold */

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